Xilinx LogiCORE IP AXI Product Manual page 36

Table 2-19: Root Port Error FIFO Read Register
Bits Name
15:0 Requester ID
17:16 Error Type
18 Error Valid
31:19 Reserved
Root Port Interrupt FIFO Read Register 1 (Offset 0x158)
Reads from this location return queued interrupt messages. Data from each read follows the
format shown in
Root Port Interrupt FIFO Read 2 register. The interrupt-handling flow should be to read this
register first, immediately followed by the Root Port Interrupt FIFO Read 2 register. For
non-Root Port cores, reads return zero.
Reads are non-destructive. Removing the message from the FIFO requires a write to either
Note:
this register or the Root Port Interrupt FIFO Read 2 register. The write value is ignored.
Table 2-20: Root Port Interrupt FIFO Read Register 1
Bits Name
15:0 Requester ID
26:16 MSI Address
28:27 Interrupt Line
29 Interrupt Assert
30 MSI Interrupt
31 Interrupt Valid
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Core Reset
Access Value
RWC 0 Requester ID belonging to the requester of the error message.
Indicates the type of the error.
00b: Correctable
RWC 0 01b: Non-Fatal
10b: Fatal
11b: Reserved
Indicates whether read succeeded.
RWC 0 1b: Success
0b: No message to read
RO 0 Reserved
Table 2-20. For MSI interrupts, the message payload is presented in the
Core Reset
Access Value
RWC 0 Requester ID belonging to the requester of the error message.
For MSI interrupts, contains address bits 12:2 from the TLP
RWC 0
address field.
Indicates interrupt line used.
00b: INTA
01b: INTB
RWC 0
10b: INTC
11b: INTD
For MSI, this field is set to 00b and should be ignored.
Indicates assert or deassert for INTx.
1b: Assert
RWC 0
0b: Deassert
For MSI, this field is set to 0b and should be ignored.
Indicates whether interrupt is MSI or INTx.
RWC 0
1b = MSI, 0b = INTx.
Indicates whether read succeeded.
RWC 0 1b: Success
0b: No interrupt to read
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Chapter 2: Product Specification
Description
Description
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