Xilinx LogiCORE IP AXI Product Manual page 103

Table B-1: Ports Used for Transceiver Debug (Cont'd)
Port
pipe_sync_fsm_tx
pipe_sync_fsm_rx
pipe_drp_fsm
pipe_rst_idle
pipe_qrst_idle
pipe_rate_idle
PIPE_DEBUG_0/gt_txresetdone
PIPE_DEBUG_1/gt_rxresetdone
PIPE_DEBUG_2/gt_phystatus
PIPE_DEBUG_3/gt_rxvalid
PIPE_DEBUG_4/gt_txphaligndone
PIPE_DEBUG_5/gt_rxphaligndone
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Direction Width
Should be examined if pipe_rst_fsm stuck at
O 11'b10000000000, or pipe_rate_fsm stuck at
24'b000100000000000000000000.
O Deprecated.
Should be examined if pipe_rate_fsm is stuck at
O
100000000.
O Wrapper is in IDLE state if pipe_rst_idle is High.
O Wrapper is in IDLE state if pipe_qrst_idle is High.
O Wrapper is in IDLE state if pipe_rate_idle is High.
Generic debug ports to assist debug. These are generic
debug ports to bring out internal PIPE Wrapper signals,
such as raw GT signals. DEBUG_0 to DEBUGT_9 are
O
intended for per lane signals. The bus width of these
generic debug ports depends on the number of lanes
configured in the wrapper.
Generic debug ports to assist debug. These are generic
debug ports to bring out internal PIPE Wrapper signals,
such as raw GT signals. DEBUG_0 to DEBUGT_9 are
O
intended for per lane signals.The bus width of these
generic debug ports depends on the number of lanes
configured in the wrapper.
Generic debug ports to assist debug. These are generic
debug ports to bring out internal PIPE Wrapper signals,
such as raw GT signals. DEBUG_0 to DEBUG_9 are
O
intended for per lane signals. The bus width of these
generic debug ports depends on the number of lanes
configured in the wrapper.
Generic debug ports to assist debug. These are generic
debug ports to bring out internal PIPE Wrapper signals,
such as raw GT signals. DEBUG_0 to DEBUG_9 are
O
intended for per lane signals. The bus width of these
generic debug ports depends on the number of lanes
configured in the wrapper.
Generic debug ports to assist debug. These generic debug
ports bring out internal PIPE Wrapper signals, such as raw
GT signals. DEBUG_0 to DEBUG_9 are intended for per
O
lane signals. The bus width of these generic debug ports
depends on the number of lanes configured in the
wrapper.
Generic debug ports to assist debug. These generic debug
ports bring out internal PIPE Wrapper signals, such as raw
GT signals. DEBUG_0 to DEBUG_9 are intended for per
O
lane signals. The bus width of these generic debug ports
depends on the number of lanes configured in the
wrapper.
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Appendix B: Debugging
Description
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