Xilinx LogiCORE IP AXI Product Manual page 27

Table 2-7: Register Memory Map (Cont'd)
Accessibility Offset
RO 0x204
R/W 0x208 - 0x234
RO 0x238 - 0xFFF
PCIe Configuration Space Header
The PCIe Configuration Space Header is a memory aperture for accessing the core for PCIe
configuration space. For 7 series devices, this area is read-only when configured as an
Endpoint. Writes are permitted for some registers when a 7 series device is configured as a
Root Port. Special access modes can be enabled using the PHY Status/Control register. All
reserved or undefined memory-mapped addresses must return zero and writes have no
effect.
VSEC Capability Register (Offset 0x128)
The VSEC Capability register (described in
to appear as though it is a part of the underlying core configuration space. The VSEC is
inserted immediately following the last enhanced capability structure in the underlying
block. VSEC is defined in §7.18 of the PCI Express Base Specification, v1.1 (§7.19 of v2.0)
[Ref 5].
Table 2-8: VSEC Capability Register
Bits Name
15:0 VSEC Capability ID
19:16 Capability Version
Next Capability
31:20
Offset
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Contents
VSEC Header 2
AXI Base Address Translation Configuration
Registers
Reserved (zeros returned on read)
Core
Reset Value
Access
RO 0x000B
RO 0x1
RO 0x200
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Chapter 2: Product Specification
Table 2-8) allows the memory space of the core
Description
PCI-SIG® defined ID identifying this Enhanced
Capability as a Vendor-Specific capability. Hardcoded to
0x000B.
Version of this capability structure. Hardcoded to 0x1.
Offset to next capability. Hardcoded to 0x0200.
Location
AXI bridge defined
memory-mapped
space.
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