Xilinx LogiCORE IP AXI Product Manual page 19

Table 2-4: Top-Level Parameters (Cont'd)
Generic Parameter Name
C_PCIEBAR2AXIBAR_0
_SEC
G35 C_PCIEBAR_LEN_1
G36 C_PCIEBAR2AXIBAR_1
C_PCIEBAR2AXIBAR_1
_SEC
G37 C_PCIEBAR_LEN_2
G38 C_PCIEBAR2AXIBAR_2
C_PCIEBAR2AXIBAR_2
_SEC
G39 C_BASEADDR
G40 C_HIGHADDR
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Description
Defines the AXIBAR
memory space (PCIe
0: Denotes a non-secure
BAR_0) (accessible
memory space
from PCIe) to be
1: Marks the AXI memory
either secure or
space as secure
non-secure memory
mapped.
Power of 2 in the
size of bytes of PCIE 13-31
BAR_1 space
AXIBAR to which
PCIE BAR_1 is Valid AXI address
mapped
Defines the AXIBAR
memory space (PCIe
0: Denotes a non-secure
BAR_1) (accessible
memory space
from PCIe) to be
1: Marks the AXI memory
either secure or
space as secure
non-secure memory
mapped.
Power of 2 in the
size of bytes of PCIE 13-31
BAR_2 space
AXIBAR to which
PCIE BAR_2 is Valid AXI address
mapped
Defines the AXIBAR
memory space (PCIe
0: Denotes a non-secure
BAR_2) (accessible
memory space
from PCIe) to be
1: Marks the AXI memory
either secure or
space as secure
non-secure memory
mapped.
AXI4-Lite Parameters
Device base address
When
Note:
configured as an
RP, the minimum
alignment
Valid AXI address
granularity must be
256 MB. Bit [27:0]
are used for Bus
Number, Device
Number, Function
number.
Device high address Valid AXI address
www.xilinx.com
Chapter 2: Product Specification
Allowable Values Default Value VHDL Type
0x0000_0000
0x0000_0000
0xFFFF_FFFF
0x0000_0000
0 Integer
16 Integer
std_logic_
vector
0 Integer
16 Integer
std_logic_
vector
0 Integer
std_logic_
vector
std_logic_
vector
19
Send Feedback