Xilinx LogiCORE IP AXI Product Manual page 55

X-Ref Target - Figure 3-8
• Accessing Bridge PCIEBAR_1 with address 0xA00000001235FEDC on the bus for PCIe
yields 0xFE35FEDC on the AXI bus.
Example 4
This example shows the generic settings to set up a combination of two independent 32-bit
AXI BARs and two independent 64-bit BARs and address translation of AXI addresses to a
remote address space for PCIe. This setting of AXI BARs does not depend on the BARs for
PCIe within the Bridge.
In this example, where C_AXIBAR_NUM=4, the following assignments for each range are
made:
C_AXIBAR_AS_0=0
C_AXIBAR_0=0x12340000
C_AXI_HIGHADDR_0=0x1234FFFF
C_AXIBAR2PCIEBAR_0=0x5671XXXX (Bits 15-0 do not matter)
C_AXIBAR_AS_1=1
C_AXIBAR_1=0xABCDE000
C_AXI_HIGHADDR_1=0xABCDFFFF
C_AXIBAR2PCIEBAR_1=0x50000000FEDC0XXX (Bits 12-0 do not matter)
C_AXIBAR_AS_2=0
C_AXIBAR_2=0xFE000000
C_AXI_HIGHADDR_2=0xFFFFFFFF
C_AXIBAR2PCIEBAR_2=0x40XXXXXX (Bits 24-0 do not matter)
C_AXIBAR_AS_3=1
C_AXIBAR_3=0x00000000
C_AXI_HIGHADDR_3=0x0000007F
C_AXIBAR2PCIEBAR_3=0x600000008765438X (Bits 6-0 do not matter)
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 3-8: PCIe to AXI Translation
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Chapter 3: Designing with the Core
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