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Xilinx LogiCORE IP Video In to AXI4-Stream v1.0 Product Manual

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Video In to
AXI4-Stream v1.0
Product Guide
PG043 April 24, 2012

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Summary of Contents for Xilinx LogiCORE IP Video In to AXI4-Stream v1.0

  • Page 1 Video In to AXI4-Stream v1.0 Product Guide PG043 April 24, 2012...

  • Page 2: Table Of Contents

    Transceiver Placement ............28 Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...
  • Page 3 Xilinx Resources ........
  • Page 4 LogiCORE IP Video In to AXI4-Stream v1.0 Introduction LogiCORE IP Facts Table Core Specifics The Xilinx LogiCORE™ IP Video In to ® ® Supported Zynq-7000, Artix-7, Virtex -7, Kintex AXI4-Stream core is designed to interface from ® Device Family Virtex-6, Spartan...

  • Page 5: Chapter 1: Overview

    DVI is an example of such a transmission mode. The Video In to AXI4-Stream core converts incoming video with explicit sync and timing to the AXI4-Stream Video protocol in order to interface to Xilinx video processing cores that use this protocol.

  • Page 6: Feature Summary

    AXI4-Stream master bus that follows the AXI4-Stream Video protocol. The core provides a pass thru of all timing signals for the Xilinx video timing controller, although the signals for the Video timing Controller are not required to pass through the Video In to AXI4 Stream core.

  • Page 7: Applications

    ° Licensing The Video In to AXI4-Stream core is provided at no cost with the Xilinx tools. Use of it is covered by the standard software license, and there are no further licensing requirements needed to use it in a design. Source code for this core is provided to enable customers to modify the core to meet their own unique requirements if necessary.

  • Page 8: Chapter 2: Product Specification

    The maximum achievable clock frequency and all resource counts can be affected by other tool options, additional logic in the FPGA device, using a different version of Xilinx tools and other factors. Refer to in Table 2-1...

  • Page 9: Resource Utilization

    For example, RGB data with 8-bits per component has a data width of 24. Table 2-1: Spartan-6 Data Width FIFO Depth LUTs RAM 16/8 Fmax (MHz) 1024 8192 33/0 Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012 Product Specification...

  • Page 10: Core Interfaces And Register Space

    The Video In to AXI4-Stream core uses industry standard control and data interfaces to connect to other system components. The following sections describe the various interfaces available with the core. Figure 2-1 illustrates an I/O diagram of the Video In to AXI4-Stream Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012 Product Specification...
  • Page 11 Not all of the timing signals are required by this core, however it also passes these signals out to a Xilinx Video Timing Controller which, depending on its configuration may require certain signal. Therefore all timing signals are present. For the Video In to AXI4 Stream core, the data enable is always required.
  • Page 12 Horizontal synch video timing signal. Active High vid_hsync vid_vblank Vertical blank video timing signal. Active High vid_hblank Horizontal blank video timing signal. Active High video_data 8-64 Parallel video input data. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012 Product Specification...
  • Page 13 The AXI4-Stream interface specification restricts TDATA widths to integer multiples of 8 bits. Therefore, in the case of data with 10 or 12 bits, data must be padded with zeros on Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012 Product Specification...
  • Page 14 The EOL pulse is 1 valid transaction wide, and must coincide with the last pixel of a scan-line, as seen in Figure 2-3. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012 Product Specification...
  • Page 15 Core Interfaces and Register Space X-Ref Target - Figure 2-3 Figure 2-3: Use of EOL and SOF Signals Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012 Product Specification...

  • Page 16: Chapter 3: Customizing And Generating The Core

    This chapter includes information on using Xilinx tools to customize and generate the core. Graphical User Interface (GUI) The Xilinx Video In to AXI4-Stream core is easily configured to meet the developer's specific needs through the CORE Generator™ GUI. This section provides a quick reference to parameters that can be configured at generation time.
  • Page 17 Hysteresis Level: Defines the “Cushion” level of the frame buffer. i.e. the number of locations that are considered the minimum fill level for FIFO operation to start. This number must be at least 16 less than the depth of the FIFO. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...

  • Page 18: Chapter 4: Designing With The Core

    Not all of the timing signals are required by this core, however it also passes these signals out to a Xilinx Video Timing Controller which, depending on its configuration may require certain timing signals. The set of timing signals used should be those required by the VTC detector.
  • Page 19 There are two external resets provided: rst, which resets the entire core, and aresetn, which resets the AXI4-Stream interface. Both resets cause the FIFO to be reset. When asserted, the reset should be held for least two clock periods of the lowest frequency clock. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...

  • Page 20: System Consideration

    AXI4-Stream interface is on the right. There are two main blocks, the data formatter and the stream coupler. The stream coupler contains an Asynchronous FIFO. These two blocks are described in detail below: Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...
  • Page 21 FIFO. Reading of the FIFO is controlled by the Output Synchronizer. The FIFO serves two primary purposes: 1. Clock domain crossing 2. Buffering of data between AXI4-Stream input and video output. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...
  • Page 22 FIFO. Note the synchronizing logic and the handshaking between clock domains. The size of the FIFO is set in the GUI when the core is generated. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...
  • Page 23 Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...
  • Page 24 Also, the level output will not necessarily be monotonic. This is taken into Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...
  • Page 25 Since the Video In to AXI4-Stream core is, by definition, at the front of the pipeline, it strives to empty its FIFO as fast as possible. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...
  • Page 26 Valid pixels get sent out on the AXI-4 Stream bus, invalid pixels do not. In this way, invalid pixels are swallowed before they get to the AXI-4 Stream bus. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...

  • Page 27: Chapter 5: Constraining The Core

    Clock Management There are two clock domains for the Video In to AXI4-Stream core. The clock crossing boundary is handled by the FIFO, and a handshaking system for passing pointers between domains. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...

  • Page 28: Clock Placement

    There are no specific Banking rules for this core. Transceiver Placement There are no Transceiver Placement requirements for this core. I/O Standard and Placement There are no specific I/O standards and placement requirements for this core. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...

  • Page 29: Chapter 6: Detailed Example Design

    Chapter 6 Detailed Example Design No example design is available at the time for the LogiCORE IP Video In to AXI4-Stream v1.0 core. Video In to AXI4-Stream www.xilinx.com PG043 April 24, 2012...

  • Page 30: Appendix A: Additional Resources

    For support resources such as Answers, Documentation, Downloads, and Forums, see the Xilinx Support website at: http://www.xilinx.com/support. For a glossary of technical terms used in Xilinx documentation, see: http://www.xilinx.com/support/documentation/sw_manuals/glossary.pdf. For a comprehensive listing of Video and Imaging application notes, white papers, reference designs and related IP cores, see the Video and Imaging Resources page at: http://www.xilinx.com/esp/video/refdes_listing.htm#ref_des.

  • Page 31: Technical Support

    The Video In to AXI4-Stream 1.0 core is provided under the Xilinx Core License Agreement and can be generated using the Xilinx® CORE Generator™ system. The CORE Generator system is shipped with Xilinx ISE® Design Suite software. Contact your local Xilinx...

  • Page 32: Notice Of Disclaimer

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

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