Chapter 2: Product Specification - Xilinx LogiCORE IP AXI Product Manual

Product Specification
Figure 2-1 shows the architecture of the AXI Bridge for PCI Express® core.
X-Ref Target - Figure 2-1
The Register block contains registers used in the AXI Bridge for PCI Express core for
dynamically mapping the AXI4 memory mapped (MM) address range provided using the
AXIBAR parameters to an address for PCIe range.
The Slave Bridge provides termination of memory-mapped AXI4 transactions from an AXI
master device (such as a processor). The Slave Bridge provides a way to translate addresses
that are mapped within the AXI4 memory mapped address domain to the domain addresses
for PCIe. When a remote AXI master initiates a write transaction to the Slave Bridge, the
write address and qualifiers are captured and write data is queued in a first in first out
(FIFO). These are then converted into one or more MemWr TLPs, depending on the
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 2-1: AXI Bridge for PCI Express Architecture
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Chapter 2
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