Xilinx LogiCORE IP AXI Product Manual page 71

X-Ref Target - Figure 4-4
Base Address Register Overview
The AXI Bridge for PCI Express core in Endpoint configuration supports up to three 32-bit
BARs or three 64-bit BARs. The AXI Memory Mapped to PCI Express® in Root Port
configuration supports one 32-bit BARs or one 64-bit BAR.
You should edit this parameter with the proper value for AXI-PCIe BAR Translation.
BARs can be one of two sizes. The selection applies to all BARs.
• 32-bit BARs: The address space can be as small as 16 bytes or as large as 2 gigabytes.
Used for Memory to I/O.
• 64-bit BARs: The address space can be as small as 128 bytes or as large as 8 exabytes.
Used for Memory only.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 4-4: PCIe Base Address Register
www.xilinx.com
Chapter 4: Design Flow Steps
Send Feedback
71