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Xilinx LogiCORE IP AXI Product Manual

Xilinx LogiCORE IP AXI Product Manual

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LogiCORE IP AXI
Bridge for PCI Express
v2.4
Product Guide
Vivado Design Suite
PG055 June 4, 2014

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Summary of Contents for Xilinx LogiCORE IP AXI

  • Page 1 LogiCORE IP AXI Bridge for PCI Express v2.4 Product Guide Vivado Design Suite PG055 June 4, 2014...

  • Page 2: Table Of Contents

    Constraining the Core ............. 77 AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback...
  • Page 3 Finding Help on Xilinx.com ........

  • Page 4: Ip Facts

    Design Entry Vivado IP integrator (MSIs) For supported simulators, see the • Legacy interrupt support Simulation Xilinx Design Tools: Release Notes Guide • Memory-mapped AXI4 access to PCIe® space Synthesis Vivado Synthesis • PCIe access to memory-mapped AXI4 space Support •...

  • Page 5: Chapter 1: Overview

    Vivado Design Suite. The AXI Bridge for PCI Express core provides an interface between an AXI4 customer user interface and PCI Express using the Xilinx Integrated Block for PCI Express. The AXI Bridge for PCI Express core provides the translation level between the AXI4 embedded system to the PCI Express system.

  • Page 6: Feature Summary

    The refclk input used by the serial transceiver for PCIe must be 100 MHz, 125 MHz, and 250 MHz for 7 series and Zynq®-7000 device configurations. The C_REF_CLK_FREQ parameter is used to set this value, as defined in Table 2-4, page AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 7: Licensing And Ordering Information

    Chapter 1: Overview Licensing and Ordering Information This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado Design Suite under the terms of the Xilinx End User License. Information about this and other Xilinx LogiCORE IP modules is available at the...

  • Page 8: Chapter 2: Product Specification

    (FIFO). These are then converted into one or more MemWr TLPs, depending on the AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 9: Standards

    AXI4-Lite interface. Standards The AXI Bridge for PCIe core is compliant with the ARM® AMBA® AXI4 Protocol Specification [Ref 4] and the PCI Express Base Specification v2.0 [Ref AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 10: Performance

    The link speed, number of lanes supported, and support of line rate for PCIe are defined in Table 2-1. Achieving line rate for PCIe is dependent on the device family, the AXI clock AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 11: Resource Utilization

    Vivado® Design Suite. Resource Utilization numbers for other devices can be generated by implementing the provided example design and checking for the resources used by only the core in the resource utilization report. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 12: Port Descriptions

    AXI Slave Interface s_axi_awid[c_s_axi_id_width-1:0] Slave write address ID s_axi_awaddr[c_s_axi_addr_width-1:0] Slave address write s_axi_awregion[3:0] Slave write region decode s_axi_awlen[7:0] Slave write burst length s_axi_awsize[2:0] Slave write burst size AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 13 Master write burst size m_axi_awburst[1:0] Master write burst type m_axi_awprot[2:0] Master write protection type m_axi_awvalid Master write address valid m_axi_awready Master write address ready m_axi_wdata[c_m_axi_data_width-1:0] Master write data AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 14 Slave write response valid s_axi_ctl_bready Slave response ready s_axi_ctl_araddr[31:0] Slave read address s_axi_ctl_arvalid Slave read address valid s_axi_ctl_arready Slave read address ready s_axi_ctl_rdata[31:0] Slave read data s_axi_ctl_rresp[1:0] Slave read response AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 15: Bridge Parameters

    Description Allowable Values Default Value VHDL Type Bridge Parameters 0: X0Y0 1: X0Y1 PCIe integrated C_PCIE_BLK_LOCN block location 2: X0Y2 String within FPGA 3: X1Y0 4: X1Y1 AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 16 C_AXIBAR_ AXI BAR_0 aperture std_logic_ (1)(3)(4) Valid AXI address 0x0000_0000 HIGHADDR_0 high address vector 0: 32 bit AXI BAR_0 address C_AXIBAR_AS_0 Integer size 1: 64 bit AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 17 PCIe BAR to which std_logic_ C_AXIBAR2PCIEBAR_4 AXI BAR_4 is Valid address for PCIe 0xFFFF_FFFF vector mapped AXI BAR_5 aperture std_logic_ (1)(3)(4) C_AXIBAR_5 Valid AXI address 0xFFFF_FFFF low address vector AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 18 Power of 2 in the C_PCIEBAR_LEN_0 size of bytes of PCIE 13-31 Integer BAR_0 space AXIBAR to which std_logic_ C_PCIEBAR2AXIBAR_0 PCIE BAR_0 is Valid AXI address 0x0000_0000 vector mapped AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 19 256 MB. Bit [27:0] are used for Bus Number, Device Number, Function number. std_logic_ C_HIGHADDR Device high address Valid AXI address 0x0000_0000 vector AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 20 IMPLEMENTED Implemented (valid only for Root Complex) 0: 100 MHz REFCLK input 1: 125 MHz C_REF_CLK_FREQ Integer Frequency 2: 250 MHz - 7 series FPGAs only AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 21 AXI Interconnect PCIe NUM_WRITE_ Slave Port Write Integer OUTSTANDING 2: Maximum of two active Pipeline Depth AXI AWADDR values can be stored in AXI slave bridge for PCIe AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 22: Parameter Dependencies

    Table 2-5: Parameter Dependencies Generic Parameter Affects Depends Description Bridge Parameters G2, G41, C_FAMILY G49, C_INCLUDE_RC Meaningful only if G1 = Kintex-7. C_COMP_TIMEOUT AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 23 AXI-memory space that is responded to by this device (AXIBAR) G19 and G20 define the range in C_AXIBAR_HIGHADDR_3 AXI-memory space that is responded to by this device (AXIBAR) AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 24 Only the high-order bits above the C_PCIEBAR2AXIBAR_1 G31, length defined by G35 are meaningful. C_PCIEBAR_LEN_2 Only the high-order bits above the C_PCIEBAR2AXIBAR_2 G31, length defined by G37 are meaningful. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 25 C_PCIE_USE_MODE. The C_PCIE_USE_MODE is used to specify the 7 series (and derivative FPGA technology) serial transceiver wrappers to use based on the silicon version. Initial Engineering Silicon (IES) as well as General Engineering Silicon (GES) must be specified. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 26: Memory Map

    Root Port Interrupt FIFO Read 1 RO - EP, R/W - RC 0x15C Root Port Interrupt FIFO Read 2 0x160 - 0x1FF Reserved (zeros returned on read) 0x200 VSEC Capability 2 AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 27 Capability as a Vendor-Specific capability. Hardcoded to 0x000B. 19:16 Capability Version Version of this capability structure. Hardcoded to 0x1. Next Capability 31:20 0x200 Offset to next capability. Hardcoded to 0x0200. Offset AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 28 ECAM Size bits dedicated to ECAM window is 20+(ECAM Size). The size of the ECAM is determined by the parameter settings of C_BASEADDR and C_HIGHADDR. 31:19 Reserved Reserved AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 29 An asserted bit in the Interrupt Decode register does not cause the interrupt line to assert IMPORTANT: unless the corresponding bit in the Interrupt Mask register is also set. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 30 PCIe was not returned within the time period selected by the Timeout C_COMP_TIMEOUT parameter. Slave Error Poison RW1C Indicates the EP bit was set in a completion TLP. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 31 (Only writable for Root Port Configurations, otherwise = ‘0’) Enables interrupts for Fatal Error events when bit is set. Fatal (Only writable for Root Port Configurations, otherwise = ‘0’) 15:12 Reserved Reserved AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 32 Bus number of port for PCIe. For Endpoint, this register is RO and 15:8 Bus Number is set by the external Root Port. 23:16 Port Number Sets the Port number field of the Link Capabilities register. 31:24 Reserved Reserved AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 33 • 0b: 2.5 GT/s • 1b: 5.0 GT/s Specifies link reliability or autonomous for directed link change operation. Directed Link Autonomous • 0b: Link reliability • 1b: Autonomous AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 34 RW1C interrupt message was dropped. Writing a 1 clears the overflow Overflow status Completion 27:20 Sets the timeout counter size for Completion Timeouts. Timeout 31:28 Reserved Reserved. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 35 Table 2-19. For EP configurations, read returns zero. Reads are non-destructive. Removing the message from the FIFO requires a write. The write value is ignored. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 36 Indicates whether interrupt is MSI or INTx. MSI Interrupt 1b = MSI, 0b = INTx. Indicates whether read succeeded. Interrupt Valid 1b: Success 0b: No interrupt to read AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 37 VSEC structure, as well as its revision and length. This register is only included if C_INCLUDE_BAR_OFFSET_REG = 1. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 38 0x214 31-0 AXIBAR2PCIEBAR_1L AXIBAR2PCIEBAR_2U 0x218 31-0 0x21C 31-0 AXIBAR2PCIEBAR_2L 0x220 31-0 AXIBAR2PCIEBAR_3U AXIBAR2PCIEBAR_3L 0x224 31-0 0x228 31-0 AXIBAR2PCIEBAR_4U 0x22C 31-0 AXIBAR2PCIEBAR_4L 0x230 31-0 AXIBAR2PCIEBAR_5U AXIBAR2PCIEBAR_5L 0x234 31-0 AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 39 = 0x00000000 To create the address for PCIe–this is the Lower 31-0 C_AXIBAR2PCIEBAR_4(31 to 0) value substituted for the least significant Address 32 bits of the AXI address. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 40 SLVERR response on the AXI4-Lite bus. When the AXI Bridge for PCIe is configured for EP AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 41 Advanced Error Reporting (AER) is not supported in the AXI Bridge for PCI Express core. The AER register space is not accessible in the AXI Bridge for PCI Express memory mapped space. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 42: Chapter 3: Designing With The Core

    This chapter includes guidelines and additional information to make designing with the core easier. General Design Guidelines The Xilinx® Vivado® Design Suite has been optimized to provide a starting point for designing with the AXI Bridge for PCI Express® core. Clocking Figure 3-1 shows the clocking diagram for the core.

  • Page 43: Resets

    Be sure to set the correct polarity on the aux_reset_in signal of the proc_sys_reset ip Note: block. when is active-Low, set the parameter as follows: PERSTN PARAMETER C_AUX_RESET_HIGH = 0 X-Ref Target - Figure 3-2 Figure 3-2: System Reset Connection AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 44: Shared Logic

    You also have the option to modify and use the unused outputs of the MMCM. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 45 The MMCM instantiated in the PCIe example design has two unconnected outputs: clkout5, and clkout6. You can use those outputs to generate other desired clock frequencies by selecting the appropriate CLKOUT5_DIVIDE and CLKOUT6_DIVIDE parameters for MMCM. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 46 PCIe uses CPLL inside GT_CHANNEL Artix7 – PCIe Gen2 GTP_COMMON has 2 QPLLs. PCIe Pipe Wrappers use only one QPLL. The remaining one can be used by shared IP core. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 47 You can share both GT_COMMON and Clocking instances when you select Include Shared Logic (Clocking) in example design and Include Shared Logic (Transceiver GT_COMMON) in example design in the Shared Logic page (see Figure 3-5). AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 48 (not brought up to the support wrapper). It can be enabled when you select Include Shared Logic in Core in the Shared Logic page (see Figure 3-6). AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 49 Chapter 3: Designing with the Core X-Ref Target - Figure 3-6 Figure 3-6: Internal Shared Logic AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 50: Axi Transactions For Pcie

    MMCM reset port. This port could be used by the upper layer to reset MMCM if error recovery is required. If the system detects the deassertion of MMCM lock, Xilinx recommends that you reset the MMCM. The recommended approach is to reset the...

  • Page 51: Transaction Ordering For Pcie

    Read data from a remote AXI slave is not permitted to pass any remote AXI master writes to a remote PCIe device initiated on the AXI bus prior to or simultaneously with AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 52: Address Translation

    32-bit AXI BARs and two 64 bit AXI BARs, and translate the AXI address to an address for PCIe. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 53 Accessing the Bridge AXIBAR_1 with address 0xABCDF123 on the AXI bus yields 0xFEDC1123 on the bus for PCIe. • Accessing the Bridge AXIBAR_2 with address 0xFFFEDCBA on the AXI bus yields 0x41FEDCBA on the bus for PCIe. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 54 BAR 1 is set to 0xA000000012000000 by Root Port C_PCIEBAR_LEN_1=25 C_PCIEBAR2AXIBAR_1=0xFEXXXXXX (Bits 24-0 do not matter) • Accessing the Bridge PCIEBAR_0 with address 0x20000000_ABCDFFF4 on the bus for PCIe yields 0x1234_7FF4 on the AXI bus. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 55 C_AXIBAR_AS_1=1 C_AXIBAR_1=0xABCDE000 C_AXI_HIGHADDR_1=0xABCDFFFF C_AXIBAR2PCIEBAR_1=0x50000000FEDC0XXX (Bits 12-0 do not matter) C_AXIBAR_AS_2=0 C_AXIBAR_2=0xFE000000 C_AXI_HIGHADDR_2=0xFFFFFFFF C_AXIBAR2PCIEBAR_2=0x40XXXXXX (Bits 24-0 do not matter) C_AXIBAR_AS_3=1 C_AXIBAR_3=0x00000000 C_AXI_HIGHADDR_3=0x0000007F C_AXIBAR2PCIEBAR_3=0x600000008765438X (Bits 6-0 do not matter) AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 56: Interrupts

    Mask & Interrupt Decode registers is used to indicate the receipt of a Message Signaled Interrupt only when the bridge is operating in Root Port mode (C_INCLUDE_RC=1). AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 57 Table 3-5. Table 3-5: MSI Vectors Enabled in Message Control Register Value Number of Messages Requested Output Signal, MSI_Vector_Width (2:0) “000” “001” “010” “011” “100” “101” AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 58: Malformed Tlp

    Slave Bridge abnormal conditions are classified as: Illegal Burst Type and Completion TLP Errors. The following sections describe the manner in which the Bridge handles these errors. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 59 When a completion timeout occurs, a Slave Completion Timeout (SCT) interrupt is asserted and the SLVERR response is asserted with arbitrary data on the memory mapped AXI4 bus. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 60 Read returned SLVERR response given with arbitrary read data. Master Bridge Abnormal Conditions The following sections describe the manner in which the Master Bridge handles abnormal conditions. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 61 LastBE = 0x00, it responds by sending a completion with Status = Successful Completion. When the Master Bridge receives a write request with the Length = 0x1, FirstBE = 0x00, and LastBE = 0x00 there is no effect. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 62: Root Port

    Root Port operation as supported by the underlying block. There are a few details that need special consideration. The following subsections contain information and design considerations about Root Port support. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 63 To receive upstream traffic from a connected device, the Root Ports PCIe BAR_0 must be configured. If BAR_0 is not configured, the Root Port responds to requests with a Completion returned with Unsupported Request status. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 64 SLVERR response is asserted Bus number in the range of secondary bus number Config Write through subordinate bus number and UR is SLVERR response is asserted returned. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 65: Chapter 4: Design Flow Steps

    IP core using the following steps: 1. Select the IP from the IP catalog. 2. Double-click the selected IP, or select the Customize IP command from the toolbar or right-click menu. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 66 X-Ref Target - Figure 4-1 Figure 4-1: Basic Parameter Settings AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 67 Clocking, page 42 for more information on clocking options. Silicon Type Selects the silicon type. PCIe Link Configuration The PCIe Link Config page is shown in Figure 4-2. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 68 Higher link speed cores are capable of training to a lower link speed if connected to a lower link speed capable device. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 69 2.5 Gb/s, 5 Gb/s 2.5 Gb/s, 5 Gb/s PCIe Block Location The AXI Bridge for PCI Express core allows the selection of the PCI Express Hard Block within Xilinx FPGAs. PCIe ID Settings The Identity Settings pages are shown in Figure 4-3.
  • Page 70 Chapter 4: Design Flow Steps unique. The default value, 10EEh, is the Vendor ID for Xilinx. Enter your vendor identification number here. FFFFh is reserved. • Device ID: A unique identifier for the application; the default value, which depends on the configuration selected, is 70<link speed><link width>h.
  • Page 71 Used for Memory to I/O. • 64-bit BARs: The address space can be as small as 128 bytes or as large as 8 exabytes. Used for Memory only. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 72 For best results, disable unused base address registers to conserve system resources. A base address register is disabled by deselecting unused BARs in the Vivado IDE. PCIe Miscellaneous The PCIe Misc screen is shown in Figure 4-5. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 73 Dynamic Slave Bridge Address Translation Enables the address translation vectors within the AXI Bridge for PCI Express bridge logic to be changed dynamically through the AXI Lite interface. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 74 BAR. Aperture Base Address Sets the base address for the address range associated to the BAR. You should edit this parameter to fit design requirements. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 75 AXI System The AXI System screen shown in Figure 4-7 sets the AXI Addressing and AXI Interconnect parameters. X-Ref Target - Figure 4-7 Figure 4-7: AXI System Settings AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 76 Enables you to share common blocks across multiple instantiations by selecting one or more of the options on this page. For a details description of the shared logic feature, see Shared Logic in Chapter AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 77: Constraining The Core

    (LOC) constraints are needed that are board/part/package specific. Placement Constraints for more details on the constraint paths for FPGA architectures. Additional information on clocking can be found in the Xilinx Solution Center for PCI Express (see Solution Centers, page 88).

  • Page 78: Placement Constraints

    Chapter 4: Design Flow Steps Placement Constraints The AXI Bridge for PCI Express core provides a Xilinx design constraint (XDC) file for all supported PCIe, Part, and Package permutations. You can find the generated XDC file in the Sources tab of the Vivado IDE after generating the IP in the Customize IP dialog box.

  • Page 79: Simulation

    “Implementing IP” in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref • For information regarding implementing the example design, see Implementation Design Overview in Chapter AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 80: Chapter 5: Example Design

    PCI Express core configured as an Endpoint and processed inside the AXI BRAM controller design. Figure 5-1 illustrates the simulation design provided with the AXI Bridge for PCI Express core. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 81: Simulating The Example Design

    Simulating the Example Design The example design can be run in any configuration using: • Vivado Simulator • Cadence IES Simulator • Mentor Graphics Questa® SIM • VCS Simulator AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 82 4. Go to the vcs_mx directory on the terminal, and run the ./board_sim_vcs_mx.sh command. Simulation is not supported for configurations with the Silicon Revision option set to IES. IMPORTANT: Only implementation is supported. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 83: Implementation Design Overview

    An example Verilog HDL or VHDL wrapper (instantiates the cores and example design). • A customizable demonstration test bench to simulate the example design. Example Design Output Structure Figure 5-2 provides the output structure of the example design. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 84 Contains block RAM controller files used axi_pcie_0_example.srcs/sources_1/ip/ in example design. axi_bram_ctrl_0 project_1/axi_pcie_0_example/ Contains all RP files, cgator and PIO files. axi_pcie_0_example.srcs/sim_1/imports/ simulation/dsport AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 85 Chapter 5: Example Design Directory Description project_1/axi_pcie_0_example/ Contains the test bench file. axi_pcie_0_example.srcs/sim_1/imports/ simulation/functional project_1/axi_pcie_0_example/ Contains the example design XDC file. axi_pcie_0_example.srcs/constrs_1/imports/ example_design AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 86: Chapter 6: Test Bench

    Chapter 6 Test Bench For information about the test bench for the example design, see Chapter 5, Example Design. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 87: Appendix A: Migrating And Upgrading

    Vivado Design Suite. Parameter Changes No parameter changes. Port Changes No port changes. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 88: Appendix B: Debugging

    Extensive debugging collateral is available in AR: 56802. Answer Records Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. AXI Bridge for PCI Express v2.4 www.xilinx.com...

  • Page 89: Contacting Technical Support

    LogiCORE™ IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.

  • Page 90: Debug Tools

    See Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 11]. Reference Boards Various Xilinx development boards support the AXI Bridge for PCI Express core. These boards can be used to prototype designs and establish that the core can communicate with the system. •...
  • Page 91 ID specified (omit the -d option to display information for all devices). The default Vendor/Device ID for Xilinx cores is 10EE:6012. Here is a sample of a read of the configuration space of a Xilinx device: >...
  • Page 92 HWDIRECT can be purchased at www.eprotek.com and allows you to view the PCI Express device configuration space as well as the extended configuration space (including the AER registers on the root). AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 93 Figure B-2: HWDIRECT with Read of Configuration Space PCI-SIG Software Suites PCI-SIG® software suites such as PCIE-CV can be used to test compliance with the specification. This software can be downloaded at www.pcisig.com. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 94: Simulation Debug

    The simulation debug flow for Mentor Graphics Questa® SIM is illustrated in Figure B-3. A similar approach can be used with other simulators. X-Ref Target - Figure B-3 Figure B-3: Questa SIM Simulation Debug Flow AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 95: Hardware Debug

    This section provides debug flow diagrams for some of the most common issues. Endpoints that are shaded gray indicate that more information is found in sections after Figure B-4. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 96 LTSSM state machine sequences outlined in Chapter 4 of the PCI Express Base Specification. Figure B-4: Design Fails in Hardware Debug Flow Diagram AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 97 100 ms window as the power supply is normally valid before the 100 ms window starts. Link is Training Debug Figure B-5 shows the flowchart for link trained debug. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 98 Device initialization and configuration issues can be caused by not having the FPGA configured fast enough to enter link training and be recognized by the system. Section 6.6 AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 99 Maintain a separation of at least 25 mils from the nearest aggressor signals. The PCI Special Interest Group website provides other tools for ensuring the reference clocks are compliant to the requirements of the PCI Express Specification: www.pcisig.com/ specifications/pciexpress/compliance/compliance_library. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...
  • Page 100 Appendix B: Debugging Debugging PCI Configuration Space Parameters Often, a user application fails to be recognized by the system, but the Xilinx PIO Example design works. In these cases, the user application is often using a PCI configuration space setting that is interfering with the system systems ability to recognize and allocate resources to the card.
  • Page 101 Appendix B: Debugging Data Transfer Failing Debug Figure B-6 shows the flowchart for data transfer debug. X-Ref Target - Figure B-6 Figure B-6: Data Transfer Debug Flow Diagram AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 102: Transceiver Debug

    Next Steps If the debug suggestions listed previously do not resolve the issue, open a support case or visit the Xilinx User Community forums to have the appropriate Xilinx expert assist with the issue. To create a technical support case in WebCase, see the Xilinx website at: www.xilinx.com/support/clearexpress/websupport.htm...
  • Page 103 GT signals. DEBUG_0 to DEBUG_9 are intended for per PIPE_DEBUG_5/gt_rxphaligndone lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 104: Interface Debug

    Ensure that the main core clocks are toggling and that the enables are also asserted. • Has a simulation been run? Verify in simulation and/or a Vivado lab tools capture that the waveform is correct for accessing the AXI4-Lite interface. AXI Bridge for PCI Express v2.4 www.xilinx.com Send Feedback PG055 June 4, 2014...

  • Page 105: Appendix C: Additional Resources And Legal Notices

    Xilinx Resources For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support. For a glossary of technical terms used in Xilinx documentation, see the Xilinx Glossary. References This section provides links to supplemental material useful to this document: 1.

  • Page 106: Revision History

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
  • Page 107 Xilinx's Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

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