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Example 2 (64-bit PCIe Address Mapping)
This example shows the generic settings to set up to three independent 64-bit AXI BARs
and address translation of AXI addresses to a remote address space for PCIe. This setting of
AXI BARs does not depend on the BARs for PCIe within the Bridge.
In this example, where C_AXIBAR_NUM=3, the following assignments for each range are
made:
C_AXIBAR_AS_0=1
C_AXIBAR_0=0x12340000
C_AXI_HIGHADDR_0=0x1234FFFF
C_AXIBAR2PCIEBAR_0=0x500000005671XXXX (Bits 15-0 do not matter)
C_AXIBAR_AS_1=1
C_AXIBAR_1=0xABCDE000
C_AXI_HIGHADDR_1=0xABCDFFFF
C_AXIBAR2PCIEBAR_1=0x60000000FEDC0XXX (Bits 12-0 do not matter)
C_AXIBAR_AS_2=1
C_AXIBAR_2=0xFE000000
C_AXI_HIGHADDR_2=0xFFFFFFFF
C_AXIBAR2PCIEBAR_2=0x7000000040XXXXXX (Bits 24-0 do not matter)
•
Accessing the Bridge AXIBAR_0 with address 0x12340ABC on the AXI bus yields
0x5000000056710ABC on the bus for PCIe.
•
Accessing the Bridge AXIBAR_1 with address 0xABCDF123 on the AXI bus yields
0x60000000FEDC1123 on the bus for PCIe.
•
Accessing the Bridge AXIBAR_2 with address 0xFFFEDCBA on the AXI bus yields
0x7000000041FEDCBA on the bus for PCIe.
Example 3
This example shows the generic settings to set up two independent BARs for PCIe and
address translation of addresses for PCIe to a remote AXI address space. This setting of
BARs for PCIe does not depend on the AXI BARs within the bridge.
In this example, where C_PCIEBAR_NUM=2, the following range assignments are made:
BAR 0 is set to 0x20000000_ABCD8000 by the Root Port
C_PCIEBAR_LEN_0=15
C_PCIEBAR2AXIBAR_0=0x1234_0XXX (Bits 14-0 do not matter)
BAR 1 is set to 0xA000000012000000 by Root Port
C_PCIEBAR_LEN_1=25
C_PCIEBAR2AXIBAR_1=0xFEXXXXXX (Bits 24-0 do not matter)
•
Accessing the Bridge PCIEBAR_0 with address 0x20000000_ABCDFFF4 on the bus for
PCIe yields 0x1234_7FF4 on the AXI bus.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
www.xilinx.com
Chapter 3: Designing with the Core
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