Xilinx LogiCORE IP AXI Product Manual page 96

X-Ref Target - Figure B-4
Using probes, an LED, Vivado lab
tools or some other method,
determine ifuser_lnk_up is asserted.
Whenuser_lnk_up is High, it
indicates the core has achieved link
up meaning the LTSSM is in L0
state and the data link layer is in the
DL_Active state.
To eliminate FPGA configuration
as a root cause, perform a soft
restart of the system. Performing a
soft reset on the system will keep
power applied and forces
re-enumeration of the device.
One reason user_reset stays
asserted other than the system
reset being asserted is due to a
faulty clock. This might keep the
PLL from locking which holds
user_reset asserted.
Multi-lane links are susceptible to
crosstalk and noise when all lanes
are switching during training.
A quick test for this is forcing one
lane operation. This can be done
by using an interposer or adapter
to isolate the upper lanes or use
a tape such as Scotch tape and
tape off the upper lanes on the
connector. If it is an embedded
board, remove the AC capacitors if
possible to isolate the lanes.
The Vivado lab tools can be used to
determine the point of failure.
Figure B-4: Design Fails in Hardware Debug Flow Diagram
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Design Fails in Hardware
Is user_lnk_up asserted?
(user_lnk_up = 1)
No
Does a soft reset fix the problem?
(user_lnk_up = 1)
No
Is user_reset deasserted?
(user_reset = 0)
Yes
Is it a multi-lane link?
No
Do you have a link analyzer?
No
www.xilinx.com
Yes
See "Link is Training Debug" section.
Yes
See "FPGA Configuration Time
Debug" section.
No
See "Clock Debug" section.
Yes
Force x1 Operation
Does user_lnk_up = 1 when using
as x1 only?
There are potentially issues
with the board layout causing
interference when all lanes are
Yes
switching. See board debug
suggestions.
Use the link analyzer to monitor the training
sequence and to determine the point of failure.
Have the analyzer trigger on the first TS1 that it
recognizes and then compare the output to the
LTSSM state machine sequences outlined in
Chapter 4 of the PCI Express Base Specification.
Appendix B: Debugging
96
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