Xilinx LogiCORE IP AXI Product Manual page 69

Table 4-2: Lane Width and Link Speed
Lane Width
x1
x2
x4
x8
PCIe Block Location
The AXI Bridge for PCI Express core allows the selection of the PCI Express Hard Block within
Xilinx FPGAs.
PCIe ID Settings
The Identity Settings pages are shown in
values and device class code.
X-Ref Target - Figure 4-3
ID Initial Values
• Vendor ID: Identifies the manufacturer of the device or application. Valid identifiers
are assigned by the PCI™ Special Interest Group to guarantee that each identifier is
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Link Speed
2.5 Gb/s, 5 Gb/s
2.5 Gb/s, 5 Gb/s
2.5 Gb/s, 5 Gb/s
2.5 Gb/s, 5 Gb/s
Figure 4-3. These settings customize the IP initial
Figure 4-3: PCIe ID Settings
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Chapter 4: Design Flow Steps
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