Xilinx LogiCORE IP AXI Product Manual page 40

Table 2-25: AXI Base Address Translation Configuration Register Bit Definitions (Cont'd)
Core
Bits Name
Access
Upper
31-0 R/W
Address
Lower
31-0 R/W
Address
Upper
31-0 R/W
Address
Enhanced Configuration Access
When the AXI Bridge for PCI Express core is configured as a Root Port, configuration traffic
is generated by using the PCI Express Enhanced Configuration Access Mechanism (ECAM).
ECAM functionality is available only when the core is configured as a Root Port. Reads and
writes to a certain memory aperture are translated to configuration reads and writes, as
specified in the PCI Express Base Specification (v1.1 and v2.1), §7.2.2
Depending on the core configuration, the ECAM memory aperture is 2
addresses. The address breakdown is defined in
memory map base address and extends to 2
the C_BASEADDR and C_HIGHADDR parameters. The number N of low-order bits of the two
parameters that do not match, specifies the 2**n byte address range of the ECAM space. If
C_INCLUDE_RC = 0, then ECAM_SIZE = 0.
When an ECAM access is attempted to the primary bus number, which defaults as bus 0
from reset, then access to the type 1 PCI™ Configuration Header of the integrated block in
the Enhanced Interface for PCIe is performed. When an ECAM access is attempted to the
secondary bus number, then type 0 configuration transactions are generated. When an
ECAM access is attempted to a bus number that is in the range defined by the secondary
bus number and subordinate bus number (not including the secondary bus number), then
type 1 configuration transactions are generated. The primary, secondary, and subordinate
bus numbers are written by Root Port software to the type 1 PCI Configuration Header of
the Enhanced Interface for PCIe in the beginning of the enumeration procedure.
When an ECAM access is attempted to a bus number that is out of the bus_number and
subordinate bus number, the bridge does not generate a configuration request and signal
SLVERR response on the AXI4-Lite bus. When the AXI Bridge for PCIe is configured for EP
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Reset Value
if (C_AXIBAR2PCIEBAR_4 = 64 bits), then
reset value = C_AXIBAR2PCIEBAR_4(63 to
32)
if (C_AXIBAR2PCIEBAR_4 = 32 bits), then
reset value = 0x00000000
C_AXIBAR2PCIEBAR_5(31 to 0)
if (C_AXIBAR2PCIEBAR_5 = 64 bits), then
reset value = C_AXIBAR2PCIEBAR_5(63 to
32)
if (C_AXIBAR2PCIEBAR_5 = 32 bits), then
reset value = 0x00000000
www.xilinx.com
Chapter 2: Product Specification
To create the address for PCIe–this is the
value substituted for the most significant
32 bits of the AXI address.
To create the address for PCIe–this is the
value substituted for the least significant
32 bits of the AXI address.
To create the address for PCIe–this is the
value substituted for the most significant
32 bits of the AXI address.
Table 2-26. The ECAM window begins at
(20+ECAM_SIZE)
- 1. ECAM_SIZE is calculated from
Description
[Ref 5].
21 28
–2 (byte)
40
Send Feedback