Xilinx LogiCORE IP AXI Product Manual page 46

Sharing the MMCM between PCIe and other cores in your design saves FPGA resources and eases
TIP:
output clock path routing.
Limitations
• Reference clock input to MMCM is restricted to 100 MHz in most use cases.
There is an option for selecting a reference clock of 125MHz or 250MHz, which is
°
not a common use case.
• The MMCM reset is tied to a static value in the top module. The MMCM can be reset as
required by the system design. Note that MMCM reset can be asserted only after
reference clock is recovered and is stable. Also, MMCM reset is indirectly tied to the
PCIe core reset and asserting MMCM reset will reset the PCIe core.
• The userclk1 and userclk2 outputs are selected based on the PCIe Lane Width,
Link Speed, and AXI width selections (for details, see
Chapter 4). Sharing cores must comply with these requirements.
Shared GT_COMMON
A quad phase-locked loop (QPLL) in GT_COMMON can serve a quad of GT_CHANNEL
instances. If the PCIe core is configured as X1 or X2 and is using a QPLL, the remaining
GT_CHANNEL instances can be used by other cores by sharing the same QPLL and
GT_COMMON.
To share GT_COMMON instances, select Include Shared Logic (Transceiver
GT_COMMON) in example design option in the Shared Logic
When this feature is selected, the GT_COMMON instance is removed from the pipe
wrappers and is moved into the support wrapper of the example design. It also brings out
additional ports to the top level to enable sharing of the GT_COMMON.
Shared logic feature for GT_COMMON helps save FPGA resources and also eases dedicated
clock routing within the single GT Quad.
Shared GT_COMMON Use Cases with GTX and GTP
Table 3-1: Shared GT_COMMON Use Cases
GT – PCIe max Link
Speed
GTX
GTP
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Device – PCIe Max Link Speed
Kintex7, Virtex7 (485T) – PCIe Gen2 PCIe Pipe Wrappers instantiate
Artix7 – PCIe Gen2
www.xilinx.com
Chapter 3: Designing with the Core
Customizing the Core in
tab(Figure
Shared GT_COMMON
GT_COMMON . Shared IP uses QPLL because
PCIe uses CPLL inside GT_CHANNEL
GTP_COMMON has 2 QPLLs. PCIe Pipe
Wrappers use only one QPLL. The remaining
one can be used by shared IP core.
Send Feedback
3-4).
46