Xilinx LogiCORE IP AXI Product Manual page 73

X-Ref Target - Figure 4-5
Interrupt Pin
Indicates the usage of Legacy interrupts.The AXI Bridge for PCI Express core implements
INTA only.
MSI Vectors Requested
Indicates the number of MSI vectors requested by the core.
Completion Timeout Configuration
Indicates the completion timeout value for incoming completions due to outstanding
memory read requests.
Dynamic Slave Bridge Address Translation
Enables the address translation vectors within the AXI Bridge for PCI Express bridge logic to
be changed dynamically through the AXI Lite interface.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 4-5: PCIe Miscellaneous
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