Simulation; Synthesis And Implementation - Xilinx LogiCORE IP AXI Product Manual

set_property LOC GTPE2_CHANNEL_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/
comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/
gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/
gtp_channel.gtpe2_channel_i}]
Also for Artix-7 devices, the GTP_COMMON must be constrained to a location. The
following LOC constraint can be utilized.
set_property LOC GTPE2_COMMON_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/
comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/
gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.qpll_wrapper_i/
gtp_common.gtpe2_common_i}]
Clock Frequencies
The AXI Memory Mapped to PCI Express Bridge supports reference clock frequencies of
100 MHz and 250 MHz and is configurable within the Vivado IDE.

Simulation

• For comprehensive information about Vivado simulation components, as well as
information about using supported third party tools, see the Vivado Design Suite User
Guide: Logic Simulation (UG900)
• For information regarding simulating the example design, see
Overview in Chapter

Synthesis and Implementation

• For details about synthesis and implementation, see "Synthesizing IP" and
"Implementing IP" in the Vivado Design Suite User Guide: Designing with IP (UG896)
[Ref 9].
• For information regarding implementing the example design, see
Design Overview in Chapter
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
[Ref 10].
5.
5.
www.xilinx.com
Chapter 4: Design Flow Steps
Simulation Design
Implementation
Send Feedback
79