Performance - Xilinx LogiCORE IP AXI Product Manual

Performance

Figure 2-2 shows a configuration diagram for a target FPGA.
X-Ref Target - Figure 2-2
MicroBlaze
Domain
MicroBlaze
Controller
D_LMB
I_LMB
Block RAM
Controller
The target FPGA is filled with logic to drive the lookup table (LUT) and block RAM utilization
to approximately 70% and the I/O utilization to approximately 80%.
Maximum Frequencies
The maximum frequency for the AXI clock is 125 MHz for 7 series FPGAs.
Line Rate Support for PCIe Gen1/Gen2
The link speed, number of lanes supported, and support of line rate for PCIe are defined in
Table 2-1. Achieving line rate for PCIe is dependent on the device family, the AXI clock
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
(IC)
MemoryMap
(DC)
Interconnect
(AXI4)
(DP)
Control
Interface
Subset
Interconnect
(AXI4-Lite)
Figure 2-2: FPGA System Configuration Diagram
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Chapter 2: Product Specification
AXI4
AXI4
Memory
Controller
AXI Block Ram
AXI PCIe
AXI CDMA
AXI INTC
AXI GPIO
AXI UARTLite
MDM
AXI4-Lite
Send Feedback
Memory
LEDs
RS232
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