Xilinx LogiCORE IP AXI Product Manual page 48

X-Ref Target - Figure 3-5
Internal Shared GT_COMMON and Clocking
This feature allows sharing of GT_COMMON and Clocks while these modules are still
internal to the core (not brought up to the support wrapper). It can be enabled when you
select Include Shared Logic in Core in the Shared Logic page (see
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 3-5: Shared GT_COMMON and Clocking
www.xilinx.com
Chapter 3: Designing with the Core
Figure 3-6).
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