Xilinx LogiCORE IP AXI Product Manual page 98

X-Ref Target - Figure B-5
FPGA Configuration Time Debug
Device initialization and configuration issues can be caused by not having the FPGA
configured fast enough to enter link training and be recognized by the system. Section 6.6
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure B-5: Link Trained Debug Flow Diagram
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Appendix B: Debugging
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