Xilinx LogiCORE IP AXI Product Manual page 25

Table 2-5: Parameter Dependencies (Cont'd)
Generic Parameter
G41 C_NO_OF_LANES
G42 C_DEVICE_ID
G43 C_VENDOR_ID
G44 C_CLASS_CODE
G45 C_REV_ID
G46 C_SUBSYSTEM_ID
G47 C_SUBSYSTEM_VENDOR_ID
C_PCIE_CAP_SLOT_
G48
IMPLEMENTED
G49 C_REF_CLK_FREQ
G50 C_M_AXI_DATA_WIDTH
G51 C_M_AXI_ADDR_WIDTH
G52 C_S_AXI_ID_WIDTH
G53 C_S_AXI_DATA_WIDTH
G54 C_S_AXI_ADDR_WIDTH
G55 C_MAX_LINK_SPEED
G56 C_INTERRUPT_PIN
Table 2-6 summarizes the relationship between the IP design parameters, C_FAMILY and
C_PCIE_USE_MODE. The C_PCIE_USE_MODE is used to specify the 7 series (and derivative
FPGA technology) serial transceiver wrappers to use based on the silicon version. Initial
Engineering Silicon (IES) as well as General Engineering Silicon (GES) must be specified.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Affects
Core for PCIe Configuration Parameters
Memory-Mapped AXI4 Bus Parameters
G53
G54
G50
G51
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Chapter 2: Product Specification
Depends Description
Parameter Setting
G1 = Kintex-7 &
G50 = G53 = 64
G1, G50,
G53
G1 = Kintex-7 &
G50 = G53 = 128
G2 If G2 = 0, G48 is not meaningful
G1
G1, G41,
G50 must be equal to G53
G53
G54 G51 must be equal to G54
G1, G41,
G53 must be equal to G50
G50
G51 G54 must be equal to G51
G1
Result
G41 = 1, 2, or 4 (Gen1),
or G41 = 1 or 2 (Gen2)
G41 = 1, 2, 4, or 8
(Gen1) or 1, 2, or 4
(Gen2)
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