Xilinx LogiCORE IP AXI Product Manual page 63

Power Limit Message TLP
The AXI Bridge for PCI Express core automatically sends a Power Limit Message TLP when
the Master Enable bit of the Command Register is set. The software must set the Requester
ID register before setting the Master Enable bit to ensure that the desired Requester ID is
used in the Message TLP.
Root Port Configuration Read
When an ECAM access is performed to the primary bus number, self-configuration of the
integrated block for PCIe is performed. A PCIe configuration transaction is not performed
and is not presented on the link. When an ECAM access is performed to the bus number
that is equal to the secondary bus value in the Enhanced PCIe type 1 configuration header,
then type 0 configuration transactions are generated.
When an ECAM access is attempted to a bus number that is in the range defined by the
secondary bus number and subordinate bus number range (not including secondary bus
number), then type 1 configuration transactions are generated. The primary, secondary and
subordinate bus numbers are written and updated by Root Port software to the type 1 PCI
Configuration Header of the AXI Bridge for PCI Express core in the enumeration procedure.
When an ECAM access is attempted to a bus number that is out of the range defined by the
secondary bus_number and subordinate bus number, the bridge does not generate a
configuration request and signal a SLVERR response on the AXI4-Lite bus.
When a Unsupported Request (UR) response is received for a configuration read request, all
ones are returned on the AXI4-Lite bus to signify that a device does not exist at the
requested device address. It is the responsibility of the software to ensure configuration
write requests are not performed to device addresses that do not exist. However, the AXI
Bridge for PCI Express core asserts SLVERR response on the AXI4-Lite bus when a
configuration write request is performed on device addresses that do not exist or a UR
response is received.
If a configuration transaction is attempted to a device number other than zero, the AXI
Bridge for PCI Express core asserts SLVERR on the AXI4-Lite bus. PCIe transactions are
generated for only the device number of zero.
Unsupported Request to Upstream Traffic
To receive upstream traffic from a connected device, the Root Ports PCIe BAR_0 must be
configured. If BAR_0 is not configured, the Root Port responds to requests with a
Completion returned with Unsupported Request status.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
www.xilinx.com
Chapter 3: Designing with the Core
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