Xilinx LogiCORE IP AXI Product Manual page 31

Table 2-12: Interrupt Decode Register (Cont'd)
Bits Name
Slave Completer
24
Abort
25 Slave Illegal Burst
26 Master DECERR
27 Master SLVERR
Master Error
28
Poison
31:29 Reserved
Interrupt Mask Register (Offset 0x13C)
The Interrupt Mask register controls whether each individual interrupt source can cause the
interrupt line to be asserted. A one in any location allows the interrupt source to assert the
interrupt line. The Interrupt Mask register initializes to all zeros. Therefore, by default no
interrupt is generated for any event.
and values.
Table 2-13: Interrupt Mask Register
Bits Name
0 Link Down
1 ECRC Error
2 Streaming Error
3 Hot Reset
4 Reserved
Cfg Completion
7:5
Status
8 Cfg Timeout
9 Correctable
10 Non-Fatal
11 Fatal
15:12 Reserved
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Core Reset
Access Value
Indicates that a completion TLP was received with a status of
RW1C 0
0b100 - Completer Abort.
Indicates that a burst type other than INCR was requested by the
RW1C 0
AXI master.
RW1C 0 Indicates a Decoder Error (DECERR) response was received.
RW1C 0 Indicates a Slave Error (SLVERR) response was received.
RW1C 0 Indicates an EP bit was set in a MemWR TLP for PCIe.
RO 0 Reserved
Table 2-13
Core Reset
Access Value
RW 0 Enables interrupts for Link Down events when bit is set.
Enables interrupts for ECRC Error events when bit is set.
RW 0
(Only writable for EP configurations, otherwise = '0')
RW 0 Enables interrupts for Streaming Error events when bit is set.
Enables interrupts for Hot Reset events when bit is set.
RW 0
(Only writable for EP configurations, otherwise = '0')
RO 0 Reserved
Enables interrupts for config completion status.
RW 0
(Only writable for Root Port Configurations, otherwise = '0')
Enables interrupts for Config (Cfg) Timeout events when bit is
RO 0 set.
(Only writable for Root Port Configurations, otherwise = '0')
Enables interrupts for Correctable Error events when bit is set.
RO 0
(Only writable for Root Port Configurations, otherwise = '0')
Enables interrupts for Non-Fatal Error events when bit is set.
RO 0
(Only writable for Root Port Configurations, otherwise = '0')
Enables interrupts for Fatal Error events when bit is set.
RO 0
(Only writable for Root Port Configurations, otherwise = '0')
RO 0 Reserved
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Chapter 2: Product Specification
Description
describes the Interrupt Mask register bits
Description
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