Resets - Xilinx LogiCORE IP AXI Product Manual

The refclk input must be provided at the frequency selected by the value of
c_ref_clk_freq. This clock is used to generate the two output clocks and is also the
clock used to drive the AXI4 bus.
The AXI4-Lite interconnect clock axi_ctl_aclk is driven by axi_ctl_aclk_out. The
axi_ctl_aclk_out clock is rising edge aligned and an integer division of the
axi_aclk_out clock.
The output clock frequency is 62.5 Mhz for x1 gen1 64-bit AXI interface, and 125 Mhz for
the remaining configurations.

Resets

The AXI Bridge for PCI Express core is designed to be used with the Processing System Reset
module for generation of the axi_areset input. When using the Vivado IP integrator to
build a system, it is best to connect the perstn pin of the host connector for PCIe to the
Aux_Reset_In port of the Processing System Reset module. The bridge does not use
perstn directly. Also, the mmcm_lock output must be connected to the dcm_locked
input of the Processing System Reset module to make sure that axi_aresetn is held
active for 16 clocks after mmcm_lock becomes active. See
Be sure to set the correct polarity on the aux_reset_in signal of the proc_sys_reset ip
Note:
block. when
PERSTN
PARAMETER C_AUX_RESET_HIGH = 0
X-Ref Target - Figure 3-2
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
is active-Low, set the parameter as follows:
Figure 3-2: System Reset Connection
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Chapter 3: Designing with the Core
Figure 3-2.
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