Xilinx LogiCORE IP AXI Product Manual page 47

Limitations
• The reset logic in the pipe wrapper resets the QPLL when the PCIe Block performs a
rate change. When sharing is enabled, the core/logic which is sharing the QPLL must be
able to handle and recover from this reset.
• The settings of the GT_COMMON should not be changed as they are optimized for the
PCIe core.
X-Ref Target - Figure 3-4
Shared GT_COMMON and Clocking
You can share both GT_COMMON and Clocking instances when you select Include Shared
Logic (Clocking) in example design and Include Shared Logic (Transceiver
GT_COMMON) in example design in the Shared Logic page (see
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 3-4: Shared GT_COMMON
www.xilinx.com
Chapter 3: Designing with the Core
Figure 3-5).
Send Feedback
47