Table of Contents
Advertisement
the read data being returned on the AXI bus. Timing is based off the AXI awvalid
signal timing relative to the AXI rvalid assertion. Any AXI write transaction in which
awvalid was asserted before or simultaneously with the rvalid being asserted up to
and including the last data beat, causes the Completion TLP(s) to be held until the
pipelined or simultaneous MemWr TLP(s) have been sent.
The transaction ordering rules for PCIe might have an impact on data throughput in
IMPORTANT:
heavy bidirectional traffic.
Address Translation
The address space for PCIe is different than AXI address space. To access one address space
from another address space requires an address translation process. On the AXI side, the
bridge supports mapping to PCIe on up to six 32-bit or 64-bit AXI base address registers
(BARs). The generics used to configure the BARs follow.
C_AXIBAR_NUM, C_AXIBAR_n, C_AXIBAR_HIGHADDR_n, C_AXIBAR2PCIEBAR_n and
C_AXIBAR_AS_n,
where n represents an AXIBAR number from 0 to 5. The bridge for PCIe supports
mapping on up to three 64-bit BARs for PCIe. The generics used to configure the BARs
are:
C_PCIEBAR_NUM, C_PCIE2AXIBAR_n and C_PCIEBAR_LEN_n,
where n represents a particular BAR number for PCIe from 0 to 2.
The C_INCLUDE_BAROFFSET_REG generic allows for dynamic address translation. When this
Note:
parameter is set to one, the AXIBAR2PCIEBAR_n translation vectors can be changed by using the
software.
Four examples follow:
•
Example 1 (32-bit PCIe Address Mapping)
BARs and translate the AXI address to an address for PCIe.
•
Example 2 (64-bit PCIe Address Mapping)
BARs and translate the AXI address to an address for PCIe.
•
Example 3
demonstrates how to set up two 64-bit PCIe BARs and translate the address
for PCIe to an AXI address.
•
Example 4
demonstrates how set up a combination of two 32-bit AXI BARs and two 64
bit AXI BARs, and translate the AXI address to an address for PCIe.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
demonstrates how to set up four 32-bit AXI
demonstrates how to set up three 64-bit AXI
www.xilinx.com
Chapter 3: Designing with the Core
Send Feedback
52
Advertisement
Table of Contents
