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Table 2-4: Top-Level Parameters (Cont'd)
Generic
Parameter Name
C_XLNX_REF_BOARD
G1
C_FAMILY
G2
C_INCLUDE_RC
G3
C_COMP_TIMEOUT
C_INCLUDE_
G4
BAROFFSET_REG
C_SUPPORTS_
G5
NARROW_BURST
G6
C_AXIBAR_NUM
G7
C_AXIBAR_0
C_AXIBAR_
G8
HIGHADDR_0
G9
C_AXIBAR_AS_0
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Description
NONE
KC705_REVA
Target FPGA Board
KC705_REVB
KC705_REVC
VC707
kintex7, virtex7, artix7,
Target FPGA Family
zynq
Configures the AXI
0: Endpoint
bridge for PCIe to be
1: Root Port (applies only
a Root Port or an
for 7 series, and
Endpoint
Zynq-7000 devices)
Selects the Slave
Bridge completion
0: 50 µs
timeout counter
1: 50 ms
value
Include the registers
for high-order bits
0: Exclude
to be substituted in
1: Include
translation in Slave
Bridge
Instantiates internal
logic to support
narrow burst
transfers. Only
0: Not supported
enable when AXI
1: Supported
master bridge
generates narrow
burst traffic.
1-6;
1: BAR_0 enabled
2: BAR_0, BAR_1 enabled
3: BAR_0, BAR_1, BAR_2
Number of AXI
enabled
address apertures
4: BAR_0 through BAR_3
that can be accessed
enabled
5: BAR_0 through BAR_4
enabled
6: BAR_0 through BAR_5
enabled
AXI BAR_0 aperture
Valid AXI address
low address
AXI BAR_0 aperture
Valid AXI address
high address
0: 32 bit
AXI BAR_0 address
size
1: 64 bit
www.xilinx.com
Chapter 2: Product Specification
Allowable Values
Default Value VHDL Type
(1)(3)(4)
0xFFFF_FFFF
(1)(3)(4)
0x0000_0000
NONE
String
String
0
Integer
0
Integer
0
Integer
0
Integer
6
Integer
std_logic_
vector
std_logic_
vector
0
Integer
16
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