I 2 C Serial Interface; I 2 C Features; I 2 C Overview; I 2 C Operation - Analog Devices ADuCM320 Hardware Reference Manual

ADuCM320 Hardware Reference Manual
2
I C SERIAL INTERFACE
2
I C FEATURES

Master or slave mode with 2-byte transmit and receive FIFOs

Supports
o
7-bit and 10-bit addressing modes
o
Four 7-bit device addresses or one 10-bit address and two 7-bit addresses in the slave
o
Repeated starts in master and slave modes
o
Clock stretching can be enabled by other devices on the bus without causing any issues with the ADuCM320; however, the
ADuCM320 cannot enable clock stretching
o
Master arbitration
o
Continuous read mode for the master or up to 512 bytes fixed read
o
Internal and external loopback

Support for DMA in master and slave modes

Software control on the slave of NACK signal
2
I C OVERVIEW
2
The I C data transfer uses a serial clock pin (SCL) and a serial data pin (SDA). The pins are configured in a wired-AND' e d format that
allows arbitration in a multimaster system.
The transfer sequence of an I
The master transmits the slave device address and the direction of the data transfer during the initial address transfer. If the master does
not lose arbitration and the slave acknowledges the initial address transfer, the data transfer is initiated. This continues until the master
issues a stop condition and the bus becomes idle. Figure 19 shows a typical I
A master device can be configured to generate the serial clock. The frequency is programmed by the user in the serial clock divisor register,
I2CxDIV (where x is 0 for I2C0 and 1 for I2C1). The master channel can be set to operate in fast mode (400 kHz) or standard mode (100 kHz).
MSB
SDA
SCL
1
START
BIT
2
The I C bus peripheral address in the I
progress. The user can set up to four slave addresses that are recognized by the peripheral. The peripheral is implemented with a 2-byte
FIFO for each transmit and receive shift register. The IRQ and status bits in the control registers are available to signal to the processor
core when the FIFOs need to be serviced.
2
I C OPERATION
2
I C Startup
The following steps are required to run the I
2
1. Configure the I C clock in CLKCON1[10:8], CLKCON5[4] for I
2. Configure digital pins (P0.4/P0.5, P0.6/P0.7) for I
2
3. Configure I C registers as required for slave or master operation.
2
4. Enable the I C slave or master interrupt source as required.
Note that the user should disable the internal pull-up resistors on the I
Table 134. GPIO Multiplex
GPIO
P0.4, P0.6
P0.5, P0.7
2
C system consists of a master device initiating a transfer by generating a start condition while the bus is idle.
SLAVE ADDRESS
3 TO 6
2 7
Figure 19. Typical I
2
C bus system is programmed by the user. This ID can be modified any time a transfer is not in
2
C peripheral:
2
C operation via the GP0CON register.
2
C transfer.
LSB MSB
R/W
8 9
ACK
BIT
2
C Transfer Sequence
2
C1, and CLKCON5[3] for I
2
C pins via the GP0PUL register when using I
Configuration Mode (01)
SCL
SDA
Rev. C | Page 101 of 196
LSB
DATA
2 TO 7
1 8 9
ACK
BIT
2
C0.
2
UG-498
STOP
BIT
C.