External Interrupt Configuration; Register Summary: External Interrupts; Register Details: External Interrupts - Analog Devices ADuCM320 Hardware Reference Manual

ADuCM320 Hardware Reference Manual

EXTERNAL INTERRUPT CONFIGURATION

Seven external interrupts are implemented. These seven external interrupts can be separately configured to detect any combination of the
following type of events:
•
Edge: rising edge, falling edge, or both rising and falling edges. An interrupt signal (pulse) is sent to the NVIC upon detecting a
transition from low to high, high to low, or on either high to low or low to high.
•
Level: high or low. An interrupt signal is generated and remains asserted in the NVIC until the conditions generating the interrupt
deassert. The level must be maintained for a minimum of one core clock cycle to be detected.
The external interrupt detection unit block is in the always-on section and allows external interrupt to wake up the device when in
hibernate mode.
Ensure that the associated GPxIE register bit is enabled for the required external interrupt input. The GPxIE register enables the input
path circuit for the external interrupt.
For example, for External Interrupt 0, the following code disables the P0.3 output and enables the input path. The appended code also
enables the External Interrupt 0 NVIC interrupt source:
pADI_GP0->GPOE &= 0xf7;
pADI_GP0->GPIE |= 0x8;
pADI_INTERRUPT->EI0CFG |= 0x8;
NVIC_EnableIRQ(EINT0_IRQn);

REGISTER SUMMARY: EXTERNAL INTERRUPTS

Table 56. External Interrupts Register Summary
Address Name
0x40002420 EI0CFG
0x40002424 EI1CFG
0x40002428 EI2CFG
0x40002430 EICLR

REGISTER DETAILS: EXTERNAL INTERRUPTS

External Interrupt Configuration Register 0
Address: 0x40002420, Reset: 0x0000, Name: EI0CFG
Table 57. Bit Descriptions for EI0CFG
Bits Bit Name
[15:12] RESERVED
11 IRQ2EN
[10:8] IRQ2MDE
7 IRQ1EN
//Disable P0.3 output.
//Enable input path for P0.3 input.
//External IRQ0 enabled.
//Enable External Interrupt 0 source.
Description
External Interrupt Configuration 0
External Interrupt Configuration 1
External Interrupt Configuration 2
External interrupt clear
Description
Reserved.
External Interrupt 2 enable bit.
0: External Interrupt 2 disabled
1: External Interrupt 2 enabled
External Interrupt 2 mode registers.
000: rising edge
001: falling edge
010: rising or falling edge
011: high level
100: low level
101: falling edge (same as 001)
110: rising or falling edge (same as 010)
111: high level (same as 011)
External Interrupt 1 enable bit.
0: External Interrupt 0 disabled
1: External Interrupt 0 enabled
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UG-498
Reset RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
Reset Access
0
0x0 RW
0x0 RW
0x0 RW