Page 1: Scope
ADuCM310 Hardware Reference Manual UG-549 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com How to Set Up and Use the ADuCM310 SCOPE This reference manual provides a detailed description of the ADuCM310 functionality and features.
Page 2: Table Of Contents
Functional Block Diagram .............. 1 Register Summary: Additional Registers ........ 32 Revision History ................4 Register Details: Additional Registers ........32 Using the ADuCM310 Hardware Reference Manual ....5 IDACs ....................34 Number Notations ................ 5 IDAC Features ................34 Register Access Conventions ............
Page 3 ADuCM310 Hardware Reference Manual UG-549 Register Summary: DMA ............73 Register Summary: SPI1 ............144 Register Details: DMA ..............73 Register Details: SPI1..............144 Flash Controller ................79 UART Serial Interface ..............148 Flash Controller Features ............79 UART Features ................148 Flash Controller Overview............
Page 4: Revision History
UG-549 ADuCM310 Hardware Reference Manual PLA Features ................185 Register Summary: PLA ............189 PLA Overview ................185 Register Details: PLA ............... 189 PLA Operation ................186 REVISION HISTORY 3/2020—Rev. B to Rev. C Added ECC Error During Read Section and ECC Error During Execution of Sign Command ..............
Page 5: Using The Aducm310 Hardware Reference Manual
ADuCM310 Hardware Reference Manual UG-549 USING THE ADuCM310 HARDWARE REFERENCE MANUAL NUMBER NOTATIONS Table 1. Notation Description Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0.
Page 6: Introduction To The Aducm310
UG-549 ADuCM310 Hardware Reference Manual INTRODUCTION TO THE ADuCM310 ADuCM310 is a triple-die stack, system on-chip designed for diagnostic control on tunable laser optical module application. The ADuCM310 features a 16-bit (14-bit no missing codes), multichannel, successive approximation register (SAR) ADC; an ARM Cortex™-M3 processor;...
Page 7: Main Features Of The Aducm310
ADuCM310 Hardware Reference Manual UG-549 MAIN FEATURES OF THE ADuCM310 • Multichannel, 14-bit, 800 kSPS SAR ADC • 14-bit no missing codes • Low drift, on-chip voltage reference DACs • Eight voltage output DACs • VDACs are 12-bit monotonic •...
Page 8: Memory Organization
UG-549 ADuCM310 Hardware Reference Manual MEMORY ORGANIZATION ADuCM310 memory organization is described in this section. Features • Cortex-M3 memory system features • Predefined memory map • Support for bit-band operation for atomic operations • Unaligned data access • ADuCM310 on-chip peripherals are accessed via memory mapped registers, situated in the bit band region.
Page 9: Clocking Architecture
ADuCM310 Hardware Reference Manual UG-549 CLOCKING ARCHITECTURE CLOCKING ARCHITECTURE FEATURES ADuCM310 integrates two on-chip oscillators and circuitry for an external crystal and external clock source: • LFOSC is a 32 kHz, low power internal oscillator that is used in low power modes.
Page 10: Clocking Architecture Overview
UG-549 ADuCM310 Hardware Reference Manual CLOCKING ARCHITECTURE OVERVIEW The system clock, UCLK can be selected from an 80 MHz PLL output (default). An external clock on P1.0 can also be used for test purposes. Internally, the system clock is divided into separate clocks: •...
Page 11 ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access [10:8] RESERVED Reserved. [7:4] CLKOUT GPIO clock out selection. 0000: UCLK. 0001: LFOSC (32 kHz). 0010: HFOSC (16 MHz). 0100: core clock (default). 0101: PCLK. 1011: General-Purpose Timer 0 clock.
Page 12 UG-549 ADuCM310 Hardware Reference Manual User Clock Gating Control Register Address: 0x40028014, Reset: 0x0040, Name: CLKCON5 The user clock gating control register (CLKCON5) controls the gates of the peripheral UCLKs. Table 7. Bit Descriptions for CLKCON5 Bits Bit Name Description...
Page 13 ADuCM310 Hardware Reference Manual UG-549 Clocking Status Register Address: 0x40028018, Reset: 0x0003, Name: CLKSTAT0 The clocking status register monitors PLL and oscillator status. Table 8. Bit Descriptions for CLKSTAT0 Bits Bit Name Description Reset Access RESERVED Reserved. Always returns 0 when read.
Page 14: Power Management Unit
UG-549 ADuCM310 Hardware Reference Manual POWER MANAGEMENT UNIT POWER MANAGEMENT UNIT FEATURES The power management unit (PMU) controls the different power modes of the ADuCM310. The following four power modes are available: • Active • CORE_SLEEP • SYS_SLEEP • Hibernate POWER MANAGEMENT UNIT OVERVIEW The Cortex-M3 sleep modes are linked to the PMU modes and are described in this section.
Page 15: Code Examples
ADuCM310 Hardware Reference Manual UG-549 CODE EXAMPLES Code Example to Enter Power Saving Modes SCB->SCR = 0x04; // sleepdeep mode pADI_PWRCTL->PWRKEY = 0x4859; // key1 pADI_PWRCTL->PWRKEY = 0xF27B; // key2 pADI_PWRCTL->PWRMOD = 0x3; // Hibernate __DSB(); __nop(); __nop(); __nop(); __nop();...
Page 16: Register Summary: Power Management Unit
UG-549 ADuCM310 Hardware Reference Manual REGISTER SUMMARY: POWER MANAGEMENT UNIT Table 9. Power Management Register Summary Address Name Description Reset Access 0x40002400 PWRMOD Power modes 0x0000 0x40002404 PWRKEY Key protection for PWRMOD 0x0000 REGISTER DETAILS: POWER MANAGEMENT UNIT Power Modes Register Address: 0x40002400, Reset: 0x0000, Name: PWRMOD Table 10.
Page 17: Arm Cortex-M3 Processor
ADuCM310 Hardware Reference Manual UG-549 ARM CORTEX-M3 PROCESSOR ARM CORTEX-M3 PROCESSOR FEATURES High Performance • 1.25 DMIPS/MHz. • Many instructions, including multiply, are single cycle. • Separate data and instruction buses allow simultaneous data and instruction accesses to be performed.
Page 18: Arm Cortex-M3 Processor Overview
• Interrupt masking In addition, the NVIC has a nonmaskable interrupt (NMI) input. The NVIC is implemented on the ADuCM310, and more details are available in the System Exceptions and Peripheral Interrupts section. Wake-Up Interrupt Controller (WIC) ADuCM310 has a modified WIC, which provides the lowest possible power-down current. More details are available in the Power Management Unit section.
Page 19: Adc Circuit
ADuCM310 Hardware Reference Manual UG-549 ADC CIRCUIT ADC CIRCUIT FEATURES ADuCM310 incorporates a fast, multichannel, 16-bit ADC. The ADC is specified to be 14-bit no missing codes. The flexible input multiplexer supports 10 external inputs and 14 internal channels. The internal channels include the following: •...
Page 20: Adc Circuit Operation
UG-549 ADuCM310 Hardware Reference Manual AIN+ AIN– OUTPUT CODE FS (V –FS (–V Figure 5. Examples of Balanced Signals for Differential Mode A high precision, low drift, factory-calibrated 2.505 V reference is provided on-chip. An external reference can also be connected to the ADC_CAPP and ADC_CAPN pins.
Page 21 ADuCM310 Hardware Reference Manual UG-549 ADCDATx[31:12] 0000 1111 1111 1111 1111 0000 1111 1111 1111 1110 0000 1111 1111 1111 1101 0000 1111 1111 1111 1100 1LSB = 65536 0000 0000 0000 0000 0011 0000 0000 0000 0000 0010 0000 0000 0000 0000 0001...
Page 22: Adc Typical Setup Sequence
IBUFCON[5:0] IBUFCON[5:0] Figure 8. ADC Input Buffer An optional input buffer can be enabled for any ADC input channel on the ADuCM310. The IBUFCON control register controls the input buffer switches as follows: • IBUFCON[1:0] controls the bypass switches on the ADC input buffer. If the input buffer is required on either the positive or negative input, the bypass switch must be turned off.
Page 23: Adc Internal Channels
ADuCM310 Hardware Reference Manual UG-549 Chopping is a common method of offset elimination on input buffers to ADCs. Chopping requires 2 × ADC conversions per measurement of a buffered ADC input channel. For example, assume that the input buffer is two input pairs: positive (+) and negative (−) input. V applied is 100 mV and the offset on the buffer is 500 µV.
Page 24: Adc Support Circuits
UG-549 ADuCM310 Hardware Reference Manual For increased accuracy, perform a two-point calibration at a controlled temperature value. The values used in this example for V and K are not guaranteed values. The values V and K vary from device to device; therefore,...
Page 25 ADuCM310 Hardware Reference Manual UG-549 ADC Channel Sequencer An ADC sequencer is provided to reduce the processor overhead of sampling and reading individual channels. The ADC sequencer allows a user to select the ADC input channels that the ADC samples, and provides a single interrupt source that is asserted when the sequence ends.
Page 26 UG-549 ADuCM310 Hardware Reference Manual ADC Voltage Reference Selection ADuCM310 integrates a low drift, 2.5 V ADC reference source. By default, this internal reference is enabled and selected as the reference source for the ADC. When using the internal 2.5 V voltage reference, ensure the following: •...
Page 27: Register Summary: Adc Circuit
ADuCM310 Hardware Reference Manual UG-549 REGISTER SUMMARY: ADC CIRCUIT The CPU accesses the ADC circuit over a die-to-die interface (D2D), which increases the execution times of ldr and str instructions. The 32-bit MMRs have 0x40086xxx addresses and require 8 CPU cycles at 80 MHz to execute. The 16-bit MMRs have 0x40082xxx addresses and require 6 CPU cycles at 80 MHz to execute.
Page 28: Register Details: Adc Circuit
UG-549 ADuCM310 Hardware Reference Manual REGISTER DETAILS: ADC CIRCUIT ADC Configuration Register Address: 0x40082174, Reset: 0x0280, Name: ADCCON Table 13. Bit Descriptions for ADCCON Bits Bit Name Description Reset Access [15:10] SOFT_RESET Software reset ADC. 0x00 ADC power up. 0: power down.
Page 29 ADuCM310 Hardware Reference Manual UG-549 ADC Channel Select Register Address: 0x40086080, Reset: 0x00111F, Name: ADCCHA ADC channel select register for nonsequence operation. Table 15. Bit Descriptions for ADCCHA Bits Bit Name Description Reset Access [15:13] RESERVED Reserved. [12:8] ADCCN Selects channel for ADC negative input.
Page 30: 3/2016-Rev. 0 To Rev. A Changes To Table 18
UG-549 ADuCM310 Hardware Reference Manual ADC Sequencer Control Register Address: 0x40086088, Reset: 0x00000000, Name: ADCSEQ Table 16. Bit Descriptions for ADCSEQ Bits Bit Name Description Reset Access Sequence restart. Forces sequence to start at first channel when sequence is working.
Page 31 ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access [9:5] DIF2 Selects differential mode negative input for AIN2 in the sequence. 0x11 0x11: Channel 2 is single-ended. [4:0] DIF0 Selects differential mode negative input for AIN0 in the sequence.
Page 32: Register Summary: Additional Registers
UG-549 ADuCM310 Hardware Reference Manual REGISTER SUMMARY: ADDITIONAL REGISTERS Table 23. Register Summary Address Name Description Reset Access 0x40083400 IBUFCON Input buffer control bit 0x000F 0x40087834 AFEREFC Reference configuration register 0x00 REGISTER DETAILS: ADDITIONAL REGISTERS Input Buffer Control Bit Register Address: 0x40083400, Reset: 0x000F, Name: IBUFCON Table 24.
Page 33 ADuCM310 Hardware Reference Manual UG-549 Reference Configuration Register Address: 0x40087834, Reset: 0x00, Name: AFEREFC Table 25. Bit Descriptions for AFEREFC Bits Bit Name Description Reset Access RESERVED Reserved. AFE_2MA_PDA Power down the 2 mA Reference Output Driving Buffer A. 0: power up 2.5 V Reference Output Driving Buffer A.
Page 34: Idacs
UG-549 ADuCM310 Hardware Reference Manual IDACs IDAC FEATURES ADuCM310 provides six IDACs: five high current DAC sources and one current source and current sink (IDAC3) channel. The current sources are low noise, low drift current outputs. • IDAC0: 0 mA to 100 mA full-scale output.
Page 35 ADuCM310 Hardware Reference Manual UG-549 IDAC3 Shutdown IDAC3 with IDAC6 are designed to control a semiconductor optical amplifier (SOA) stage of a tunable laser. IDAC3 is the main current source DAC. IDAC6 is a selectable current sink that is connected to the same external pins as IDAC3; the pin name in the ADuCM310 data sheet is IDAC3.
Page 36 UG-549 ADuCM310 Hardware Reference Manual IDAC Thermal Shutdown ADuCM310 has an internal temperature sensor that monitors the die temperature. This temperature sensor can be monitored as an ADC input channel; the measured voltage is proportional to die temperature. See the Temperature Sensor Settings section for more information.
Page 37 ADuCM310 Hardware Reference Manual UG-549 The 11-bit DAC and the 5-bit DAC are guaranteed monotonic as individual DACs. However, when combined, there is mismatch between the bit weightings of the two DACs; therefore, when combined, they are not monotonic and not even 12-bit monotonic. Nonlinearity errors occur at certain major code transitions.
Page 38 UG-549 ADuCM310 Hardware Reference Manual The following example shows how to implement this: int IdacOutC(int iChan, int iIdealVal) ADI_IDAC_TypeDef *psIDAC[6] = {pADI_IDAC0,pADI_IDAC1,pADI_IDAC2,pADI_IDAC3,pADI_IDAC4,pADI_IDAC5}; unsigned int iError; //Error as it is processed. int iSh = 0x20; iSh -= 0x08; iError = IdacCor(iChan,iIdealVal,iSh);...
Page 39 ADuCM310 Hardware Reference Manual UG-549 IDACs: Common Use Cases Case 1: Setting the Output Current of IDAC1 to Quarter Scale Set up IDAC1CON as follows: • IDAC1CON[7] = 1: enable writes to the IDAC1DAT register. • IDAC1CON[0] = 0: power up IDAC1.
Page 40: Register Summary: Idac
UG-549 ADuCM310 Hardware Reference Manual REGISTER SUMMARY: IDAC Table 27. IDAC Register Summary Address Name Description Reset Access 0x40086800 IDAC0DAT IDAC0 data register 0x00000000 0x40086804 IDAC0CON IDAC0 control register 0x01 0x40086808 IDAC1DAT IDAC1 data register 0x00000000 0x4008680C IDAC1CON IDAC1 control register...
Page 41 ADuCM310 Hardware Reference Manual UG-549 IDAC1 Data Register Address: 0x40086808, Reset: 0x00000000, Name: IDAC1DAT Table 30. Bit Descriptions for IDAC1DAT Bits Bit Name Description Reset Access [31:28] RESERVED Reserved. Write 0. [27:17] DATH IDAC1 high data. [16:12] DATL IDAC1 low data.
Page 42 UG-549 ADuCM310 Hardware Reference Manual IDAC2 Control Register Address: 0x40086814, Reset: 0x01, Name: IDAC2CON Table 33. Bit Descriptions for IDAC2CON Bits Bit Name Description Reset Access IDAC2 clear bit. 0: clear IDAC1DAT. 1: enable write. SHT_EN IDAC2 shutdown enable. Enables automatic shutdown in case of overtemperature.
Page 43 ADuCM310 Hardware Reference Manual UG-549 IDAC4 Data Register Address: 0x40086820, Reset: 0x0000000000, Name: IDAC4DAT Table 36. Bit Descriptions for IDAC4DAT Bits Bit Name Description Reset Access [31:28] RESERVED Reserved. Write 0. [27:17] DATH IDAC4 high data. [16:12] DATL IDAC4 low data.
Page 44 UG-549 ADuCM310 Hardware Reference Manual IDAC5 Control Register Address: 0x4008682C, Reset: 0x01, Name: IDAC5CON Table 39. Bit Descriptions for IDAC5CON Bits Bit Name Description Reset Access IDAC5 clear bit. 0: clear IDAC1DAT. 1: enable write. SHT_EN IDAC5 shutdown enable. Enables automatic shutdown in case of overtemperature.
Page 45 ADuCM310 Hardware Reference Manual UG-549 Table 42. HVA Register Summary Address Name Description Reset Access 0x4008E000 HVCON High voltage control 0x0000 High Voltage Control Register Address: 0x4008E000, Reset: 0x0000, Name: HVCON Table 43. Bit Descriptions for HVCON Bits Bit Name...
Page 46: Vdacs
UG-549 ADuCM310 Hardware Reference Manual VDACs VDAC FEATURES ADuCM310 has eight VDACs. Four of the VDACs are fully supported on the low voltage analog die. The other four VDACs are supported by the main DAC structure on the low voltage analog die with the output buffer circuits implemented on the high voltage analog die.
Page 47: Vdac Operation
ADuCM310 Hardware Reference Manual UG-549 VDAC OPERATION The DAC is configurable through a control register and a data register. The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, as shown in Figure 11 and Figure 12.
Page 48: 6/2019-Rev. A To Rev. B Added Table 44 Title
UG-549 ADuCM310 Hardware Reference Manual VDAC Channel 2, Channel 3, Channel 6, and Channel 7 These four VDAC channels are implemented on the low voltage analog die with the output buffer implemented on the high voltage die. The high voltage die implements the amplification and output buffer structure.
Page 49: Register Summary: Vdac
ADuCM310 Hardware Reference Manual UG-549 REGISTER SUMMARY: VDAC Table 45. VDAC Register Summary Address Name Description Reset Access 0x40082400 DAC0CON DAC0 control register 0x0100 0x40082404 DAC1CON DAC1 control register 0x0100 0x40082408 DAC2CON DAC2 control register 0x0100 0x4008240C DAC3CON DAC3 control register...
Page 50 UG-549 ADuCM310 Hardware Reference Manual DAC1 Control Register Address: 0x40082404, Reset: 0x0100, Name: DAC1CON Table 47. Bit Descriptions for DAC1CON Bits Bit Name Description Reset Access [15:11] RESERVED Reserved. DAC1_DRV DAC1 increased drive. 0: normal drive. 1: for 75 Ω load.
Page 51 ADuCM310 Hardware Reference Manual UG-549 DAC3 Control Register Address: 0x4008240C, Reset: 0x0100, Name: DAC3CON Table 49. Bit Descriptions for DAC3CON Bits Bit Name Description Reset Access [15:9] RESERVED Reserved. DAC3_PD DAC3 power down. 0: DAC3 is powered up. 1: DAC3 is powered down and output is floating.
Page 52 UG-549 ADuCM310 Hardware Reference Manual DAC5 Control Register Address: 0x40082414, Reset: 0x0100, Name: DAC5CON Table 51. Bit Descriptions for DAC5CON Bits Bit Name Description Reset Access [15:11] RESERVED Reserved. DAC5_DRV DAC5 increased drive. 0: normal drive. 1: for 300 Ω load.
Page 53 ADuCM310 Hardware Reference Manual UG-549 DAC7 Control Register Address: 0x4008241C, Reset: 0x0100, Name: DAC7CON Table 53. Bit Descriptions for DAC7CON Bits Bit Name Description Reset Access [15:9] RESERVED Reserved. DAC7_PD DAC7 power down. 0: DAC7 is powered up. 1: DAC7 is powered down and output is floating.
Page 54 UG-549 ADuCM310 Hardware Reference Manual DAC3 Data Register Address: 0x40086410, Reset: 0x00000000, Name: DAC3DAT Table 57. Bit Descriptions for DAC3DAT Bits Bit Name Description Reset Access [31:28] RESERVED Reserved. Write 0. [27:16] DAC3_DAT DAC3 data. [15:0] RESERVED Reserved. Write 0.
Page 55 ADuCM310 Hardware Reference Manual UG-549 DAC5 Data Register Address: 0x40086418, Reset: 0x00000000, Name: DAC5DAT Table 59. Bit Descriptions for DAC5DAT Bits Bit Name Description Reset Access [31:28] RESERVED Reserved. Write 0. [27:16] DAC5_DAT DAC5 data. [15:0] RESERVED Reserved. Write 0.
Page 56: System Exceptions And Peripheral Interrupts
Type Priority Description Reset −3 (highest) Any reset. −2 Nonmaskable not connected on ADuCM310. Hard fault −1 All fault conditions if the corresponding fault handler is not enabled. Memory management fault Programmable Memory management fault; access to illegal locations. Bus fault...
Page 57 ADuCM310 Hardware Reference Manual UG-549 Position Number Vector Wake Up Processor from Mode 1 Wake Up Processor from Mode 2 or Mode 3 SPI1 C0 slave C0 master PLA 0 PLA 1 DMA error DMA Channel 0 (SPI0 Tx) done...
Page 58 UG-549 ADuCM310 Hardware Reference Manual For example, to enable the PWM PAIR0 interrupt source in the NVIC, set ISER1[20] = 1. Similarly, to disable the PWM PAIR0 interrupt, set ICER1[20] = 1. Alternatively, CMSIS provides a number of useful NVIC functions in the core_cm3.h file. The NVIC_EnableIRQ(PWM_PAIR0_IRQn) function enables the PWM PAIR0 interrupt.
Page 59: External Interrupt Configuration
ADuCM310 Hardware Reference Manual UG-549 Analog Devices Address Header File Name Description Access 0xE000ED2C HFSR Hard fault status. 0xE000ED34 MMAR Memory manage fault address register. 0xE000ED38 BFAR Bus fault address. 0xE000EF00 STIR Software trigger interrupt register. EXTERNAL INTERRUPT CONFIGURATION Nine external interrupts are implemented. These nine external interrupts can be separately configured to detect any combination of the following type of events: •...
Page 60: Register Details: External Interrupts
UG-549 ADuCM310 Hardware Reference Manual REGISTER DETAILS: EXTERNAL INTERRUPTS External Interrupt Configuration Register 0 Address: 0x40002420, Reset: 0x0000, Name: EI0CFG Table 66. Bit Descriptions for EI0CFG Bits Bit Name Description Reset Access IRQ3EN External Interrupt 3 enable bit. 0: External Interrupt 3 disabled.
Page 61 ADuCM310 Hardware Reference Manual UG-549 External Interrupt Configuration Register 1 Address: 0x40002424, Reset: 0x0000, Name: EI1CFG Table 67. Bit Descriptions for EI1CFG Bits Bit Name Description Reset Access IRQ7EN External Interrupt 7 enable bit. 0: External Interrupt 7 disabled. 1: External Interrupt 7 enabled.
Page 62 UG-549 ADuCM310 Hardware Reference Manual External Interrupt Configuration Register 2 Address: 0x40002428, Reset: 0x0000, Name: EI2CFG Table 68. Bit Descriptions for EI2CFG Bits Bit Name Description Reset Access [15:4] Reserved Reserved. IRQ8EN External Interrupt 8 enable bit. 0: External Interrupt 8 disabled.
Page 63: Low Voltage Analog Die Interrupt Configuration
ADuCM310 Hardware Reference Manual UG-549 LOW VOLTAGE ANALOG DIE INTERRUPT CONFIGURATION Two interrupt lines are available between the low voltage analog die and the interrupt controller on the digital die. These two interrupt lines are the outputs of two multiplexers of multiple interrupt sources from the low voltage analog die.
Page 64: Register Details: Low Voltage Die Interrupts
UG-549 ADuCM310 Hardware Reference Manual REGISTER DETAILS: LOW VOLTAGE DIE INTERRUPTS Interrupt Clear Register Address: 0x40083004, Reset: 0x0000, Name: INTCLR Table 71. Bit Descriptions for INTCLR Bits Bit Name Description Reset Access CLR_WRECC_ERR Write 1 to this bit to clear the write ECC error interrupt flag.
Page 65: Reset
ADuCM310 Hardware Reference Manual UG-549 RESET RESET FEATURES There are four following kinds of resets: • External reset • Power-on reset • Watchdog timeout • Software system reset RESET OPERATION The software system reset is provided as part of the Cortex-M3 processor. To generate a software system reset, the NVIC_SystemReset() function must be called.
Page 66: Register Details: Reset
UG-549 ADuCM310 Hardware Reference Manual REGISTER DETAILS: RESET Reset Status Register Address: 0x40002440, Reset: 0x0000, Name: RSTSTA Table 76. Bit Descriptions for RSTSTA Bits Bit Name Description Reset Access [15:4] RESERVED Reserved. SWRST Software reset. Set automatically to 1 when the Cortex system reset is generated.
Page 67: Dma Controller
ADuCM310 Hardware Reference Manual UG-549 DMA CONTROLLER DMA FEATURES The DMA features are as follows: • 14 dedicated and independent DMA channels • Two programmable priority levels for each DMA channel • Each priority level arbitrates using a fixed priority that is determined by the DMA channel number.
Page 68: Interrupts
UG-549 ADuCM310 Hardware Reference Manual INTERRUPTS An interrupt can be produced when a transfer is complete for each DMA channel. Separate interrupt enable bits are available in the NVIC for each of the DMA channels. The DMA controller fetches channel control data structures located in the SRAM memory to perform data transfers. When enabled to use DMA operation, the DMA-capable peripherals request the DMA controller for transfer.
Page 69: Control Data Configuration
ADuCM310 Hardware Reference Manual UG-549 Example Code: Define DMA Structures memset(dmaChanDesc,0x0,sizeof(dmaChanDesc)); // Setup the DMA base address pointer register. uiBasPtr = (unsigned int)&dmaChanDesc; // Setup the DMA base pointer. pADI_DMA->DMACFG = 1; // Enable DMA controller pADI_DMA->DMAPDBPTR = uiBasPtr; CONTROL DATA CONFIGURATION For each DMA transfer, the CHNL_CFG memory location provides the control information for the DMA transfer to the controller.
Page 70: Dma Transfer Types (Chnl_Cfg[2:0])
UG-549 ADuCM310 Hardware Reference Manual Bits Name Description [25:24] SRC_SIZE Size of the source data. 00: byte. 01: half word. 10: word. 11: reserved. [23:18] Reserved Undefined. Write as 0. [17:14] R_POWER Set these bits to control how many DMA transfers can occur before the controller rearbitrates. Must be set to 0000 for all DMA transfers involving peripherals.
Page 71 ADuCM310 Hardware Reference Manual UG-549 Autorequest (CHNL_CFG[2:0] = 010) In autorequest mode, it is only necessary for the controller to receive a single request to enable it to complete the entire DMA cycle. This allows a large data transfer to occur without significantly increasing the latency for servicing higher priority requests or requiring multiple requests from the processor or peripheral.
Page 72: Address Calculation
UG-549 ADuCM310 Hardware Reference Manual Peripheral Scatter-Gather (CHNL_CFG[2:0] = 110 or 111) In peripheral scatter-gather mode, the controller must be configured to use both the primary and alternate data structure. The controller uses the primary data structure to program the control structure of the alternate data structure. The alternate data structure is used for actual data transfers, and each transfer takes place using the alternate data structure with a basic DMA transfer.
Page 73: Register Summary: Dma
ADuCM310 Hardware Reference Manual UG-549 REGISTER SUMMARY: DMA Table 86. DMA Register Summary Address Name Description Reset Access 0x40010000 DMASTA DMA status 0x000F0000 0x40010004 DMACFG DMA configuration 0x00000000 0x40010008 DMAPDBPTR DMA channel primary control data base pointer 0x00000000 0x4001000C DMAADBPTR...
Page 74 UG-549 ADuCM310 Hardware Reference Manual DMA Configuration Register Address: 0x40010004, Reset: 0x00000000, Name: DMACFG Table 88. Bit Descriptions for DMACFG Bits Bit Name Description Reset Access [31:1] RESERVED Reserved. Undefined. MENABLE Controller enable. 0: disable controller. 1: enable controller. DMA Channel Primary Control Data Base Pointer Register Address: 0x40010008, Reset: 0x00000000, Name: DMAPDBPTR The DMAPDBPTR register must be programmed to point to the primary channel control base pointer in the system memory.
Page 75 ADuCM310 Hardware Reference Manual UG-549 DMA Channel Request Mask Set Register Address: 0x40010020, Reset: 0x00000000, Name: DMARMSKSET Table 92. Bit Descriptions for DMARMSKSET Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. Reads back 0. [13:0] CHREQMSET Mask requests from DMA channels. This register disables DMA requests from peripherals.
Page 76 UG-549 ADuCM310 Hardware Reference Manual DMA Channel Enable Clear Register Address: 0x4001002C, Reset: 0x00000000, Name: DMAENCLR Table 95. Bit Descriptions for DMAENCLR Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. Undefined. [13:0] CHENCLR Disable DMA channels. This register allows the disabling of DMA channels.
Page 77 ADuCM310 Hardware Reference Manual UG-549 DMA Channel Priority Set Register Address: 0x40010038, Reset: 0x00000000, Name: DMAPRISET Table 98. Bit Descriptions for DMAPRISET Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. Undefined. [13:0] CHPRISET Configure channel for high priority. This register enables the user to configure a DMA channel to use the high priority level.
Page 78: Changes To Protection, Integrity Section
UG-549 ADuCM310 Hardware Reference Manual DMA Channel Bytes Swap Enable Set Register Address: 0x40010800, Reset: 0x00000000, Name: DMABSSET Table 101. Bit Descriptions for DMABSSET Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. Undefined. [13:0] CHBSWAPSET Byte swap status. This register configures a DMA channel to use the byte.
Page 79: Flash Controller
ADuCM310 Hardware Reference Manual UG-549 FLASH CONTROLLER FLASH CONTROLLER FEATURES The flash controller features are as follows: • 256 kB Flash/EE memory in 2 blocks of 128 kB each (Flash 0 and Flash 1) • 4 kB information space, which contains factory code FLASH CONTROLLER OVERVIEW The flash controller supports read on one flash block and erase/write operation on the other block.
Page 80: Flash Controller Operation
The information space of Flash 0 and Flash 1 is located at Address 0x40000 to Address 0x40FFF and is divided up between kernel space, test space, and calibration space. Information space is reserved for use by Analog Devices, Inc. Upon reset, the hardware forces the device to execute from the start of information space to copy calibration and configuration values to appropriate MMRs.
Page 81: Flash Memory Operation
ADuCM310 Hardware Reference Manual UG-549 FLASH MEMORY OPERATION Keyhole Access Writing to flash is through keyhole access. Keyhole access consists of the following: • Flash address • Flash data MMR • Command MMR Top of Flash Blocks The top six words of each flash block have special functionality as listed in Figure 16 and Figure 17. Therefore, normal code or data cannot be placed here.
Page 82: Added Ecc Error During Read Section And Ecc Error During Execution Of Sign Command
UG-549 ADuCM310 Hardware Reference Manual Signature The signature checks the integrity of the flash device. The signature is calculated from the lowest 32-bit word to the second highest 32-bit word in the selected block. The signature is a 24-bit CRC with an initial value of 0xFFFFFF and the following polynomial: + x + 1 The data is pushed into the CRC polynomial until the specified end address is reached.
Page 83 (USERFAAKEY). The user must set the key as two 32-bit values near the top of each user flash block. Supplying this key to Analog Devices allows access to user code for debug purposes.
Page 84 UG-549 ADuCM310 Hardware Reference Manual Flash Controller Abort Commands (erase, sign, or mass verify) and writes can be aborted upon receipt of an interrupt as listed in Table 63. Aborts are also possible by writing an abort command to the FEECMD register. However, if flash is being programmed and the routine controlling the programming is in flash, it is not possible to use the abort command to abort the cycle because instructions cannot be read.
Page 85 ADuCM310 Hardware Reference Manual UG-549 CPU Execution Speed The basic execution speed of the ADuCM310 is one CPU cycle per clock cycle. The default clock speed is 80 MHz. This speed is achieved when running from cache but is slightly less when running directly from flash. An average execution speed of over 70 MHz is typically achieved for typical C code.
Page 86: Changes To Table 104
UG-549 ADuCM310 Hardware Reference Manual Flash DMA Support Flash controller operations can be supported by DMA. This feature is software configurable. The two flash blocks are independent, meaning that the user can continue executing from one block while programming another block. The DMA is very useful for this because the core must only initiate the write to flash and the DMA takes care of it in the background, triggering an interrupt when the operation is complete.
Page 87: Register Summary: Flash Controller
ADuCM310 Hardware Reference Manual UG-549 Flash Controller Performance and Command Duration All flash functions are slower than the CPU execution speed. The CPU Execution Speed section details the slight penalty of slower flash reads. All other flash operations are significantly slower, as detailed in Table 103.
Page 88: Register Details: Flash Controller
UG-549 ADuCM310 Hardware Reference Manual REGISTER DETAILS: FLASH CONTROLLER Status Register Address: 0x40018000, Reset: 0x00000000, Name: FEESTA Table 105. Bit Descriptions for FEESTA Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. [28:27] ECCREADERRIBUS Instruction bus ECC error during a read of flash if a system exception is enabled.
Page 89 ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access SIGNERR Information space signature check on reset error. After a reset, the flash controller automatically checks the information space signature. If the signature check fails, this bit is asserted. The user can check if this bit is set via serial wire only.
Page 90 UG-549 ADuCM310 Hardware Reference Manual Bits Bit Name Description Reset Access WRCLOSE This bit is asserted when the user has written all keyhole registers for flash write, and the controller has started the write. If this bit is high, all keyhole registers (FEEFLADR, FEEFLDATA0, FEEFLDATA1), except the command register (FEECMD), are closed for write.
Page 91 ADuCM310 Hardware Reference Manual UG-549 Command Register Address: 0x40018008, Reset: 0x00000000, Name: FEECMD Table 107. Bit Descriptions for FEECMD Bits Bit Name Description Reset Access [31:5] RESERVED Returns 0x0. Always returns 0 when read. [4:0] 00000: IDLE. No command executed.
Page 92 UG-549 ADuCM310 Hardware Reference Manual Flash Address Keyhole Register Address: 0x4001800C, Reset: 0x00000000, Name: FEEFLADR Table 108. Bit Descriptions for FEEFLADR Bits Bit Name Description Reset Access [31:19] RESERVED Returns 0x0 if read. [18:3] FLADDR Memory mapped address for the flash location. Specifies flash address for write command.
Page 93: Added Ecc Enable/Disable, Error Response Register Section And Table 121; Renumbered Sequentially
ADuCM310 Hardware Reference Manual UG-549 Write Protection Register For Flash 0 Address: 0x40018028, Reset: 0xFFFFFFFF, Name: FEEPRO0 Table 114. Bit Descriptions for FEEPRO0 Bits Bit Name Description Reset Access [31:0] WRPROT0 Write protection for Flash 0 − 32 bits. Each bit corresponds to a 4 kB flash 0xFFFFFFFF section.
Page 94: Added Flash 0 Ecc Error Address Register Section, Table 122, Flash 1 Ecc Error Address Register Section, And Table 123
UG-549 ADuCM310 Hardware Reference Manual Write Abort Address Register Address: 0x40018040, Reset: 0x0000000X, Name: FEEWRADDRA Table 118. Bit Descriptions for FEEWRADDRA Bits Bit Name Description Reset Access [31:0] WRABORTADDR If a write is aborted, this register contains the address of the location being written when the write was aborted.
Page 95 ADuCM310 Hardware Reference Manual UG-549 Flash 0 ECC Error Address Register Address: 0x40018074, Reset: 0x00000000, Name: FEEECCADDR0 Table 122. Bit Descriptions for FEEECCADDR0 Bits Bit Name Description Reset Access [31:19] RESERVED Reserved. [18:0] VALUE This register has the address of Flash 0 for which the ECC error is detected.
Page 96 UG-549 ADuCM310 Hardware Reference Manual Cache Setup Register Address: 0x400180C4, Reset: 0x00000002, Name: CACHESETUP This register is key protected; therefore, the key (0xF123F456) must be entered in CACHEKEY. Table 125. Bit Descriptions for CACHESETUP Bits Bit Name Description Reset Access...
Page 97: Silicon Identification
ADuCM310 Hardware Reference Manual UG-549 SILICON IDENTIFICATION ADuCM310 has three silicon die, and each die has a register that identifies the silicon. On the digital die, the CHIPID register contains the silicon version in the bottom 4 bits and, in the following 12 bits, the device identification.
Page 98: Digital Inputs/Outputs
UG-549 ADuCM310 Hardware Reference Manual DIGITAL INPUTS/OUTPUTS DIGITAL INPUTS/OUTPUTS FEATURES ADuCM310 features a number of bidirectional general-purpose input/output (GPIO) pins. Most of the GPIO pins have multiple functions, configurable by user code. At power up, all but one of these pins are configured as GPIOs; one pin reflects the state of the POR.
Page 99: Digital Inputs/Outputs Operation
ADuCM310 Hardware Reference Manual UG-549 DIGITAL INPUTS/OUTPUTS OPERATION Input/Output Pull-Up Enable All GPIO pins have an internal pull-up resistor with a drive capability of 3 mA. Using the GPxPUL register, it is possible to enable/disable pull-up registers on the pins when they are configured as inputs. The pull-ups are automatically disabled when the GPIO pin is set as an output or when open circuit is enabled.
Page 100: Digital Port Multiplex
UG-549 ADuCM310 Hardware Reference Manual DIGITAL PORT MULTIPLEX This block provides control over the GPIO functionality of specified pins because some of the pins have a choice to work as a GPIO or to have other specific functions. Table 130. GPIO Multiplex Table...
Page 101 ADuCM310 Hardware Reference Manual UG-549 Configuration Modes GPIO GP2—GP2CON Controls These Bits P2.0 GPIO/IRQ2 PWMTRIP PLACLK2 PLAI[8] (GP2CON[1:0] = 0x0) (GP2CON[1:0] = 0x1) (GP2CON[1:0] = 0x2) (GP2CON[1:0] = 0x3) P2.1 GPIO/IRQ3 PWMSYNC PLAI[9] (GP2CON[3:2] = 0x0) (GP2CON[3:2] = 0x1) (GP2CON[3:2] = 0x3) P2.2...
Page 102: Register Summary: Digital Input/Output
UG-549 ADuCM310 Hardware Reference Manual REGISTER SUMMARY: DIGITAL INPUT/OUTPUT Table 131. GPIO Register Summary Address Name Description Reset Access 0x40020000 GP0CON GPIO Port 0 configuration 0x0000 0x40020004 GP0OEN GPIO Port 0 output enable 0x00 0x40020008 GP0PUL GPIO Port 0 pull-up enable...
Page 103: Register Details: Digital Input/Output
ADuCM310 Hardware Reference Manual UG-549 REGISTER DETAILS: DIGITAL INPUT/OUTPUT GPIO Port Configuration Registers Address: 0x40020000, Reset: 0x0000, Name: GP0CON Address: 0x40020040, Reset: 0x0000, Name: GP1CON Address: 0x40020080, Reset: 0x0000, Name: GP2CON Table 132. Bit Descriptions for GP0CON, GP1CON, and GP2CON...
Page 104 UG-549 ADuCM310 Hardware Reference Manual GPIO Port Registered Data Input Registers Address: 0x40020010, Reset: 0xXX, Name: GP0IN Address: 0x40020050, Reset: 0xXX, Name: GP1IN Address: 0x40020090, Reset: 0xXX, Name: GP2IN Table 136. Bit Descriptions for GP0IN, GP1IN, and GP2IN Bits Bit Name...
Page 105 ADuCM310 Hardware Reference Manual UG-549 GPIO Port Pin Toggle Registers Address: 0x40020020, Reset: 0x00, Name: GP0TGL Address: 0x40020060, Reset: 0x00, Name: GP1TGL Address: 0x400200A0, Reset: 0x00, Name: GP2TGL Table 140. Bit Descriptions for GP0TGL, GP1TGL, and GP2TGL Bits Bit Name...
Page 106 UG-549 ADuCM310 Hardware Reference Manual GPIO Port 3 Configuration Register Address: 0x400200C0, Reset: 0x0000, Name: GP3CON Table 142. Bit Descriptions for GP3CON Bits Bit Name Description Reset Access [15:10] RESERVED Reserved. [9:8] CON4 Configuration bits for Port 3.4. See Table 130.
Page 107 ADuCM310 Hardware Reference Manual UG-549 GPIO Port 3 Input Path Enable Register Address: 0x400200CC, Reset: 0x00, Name: GP3IE This register must be set for external interrupts and to read the pin value. Table 145. Bit Descriptions for GP3IE Bits Bit Name...
Page 108 UG-549 ADuCM310 Hardware Reference Manual GPIO Port 3 Data Out Set Register Address: 0x400200D8, Reset: 0x00, Name: GP3SET Table 148. Bit Descriptions for GP3SET Bits Bit Name Description Reset Access [7:5] RESERVED Reserved. 0x00 Set the output high. Do not use the bit-band alias addresses for this register.
Page 109 ADuCM310 Hardware Reference Manual UG-549 GPIO Port 3 Pin Toggle Register Address: 0x400200E0, Reset: 0x00, Name: GP3TGL Table 150. Bit Descriptions for GP3TGL Bits Bit Name Description Reset Access [7:5] RESERVED Reserved. 0x00 Toggle the output of the port pin. Do not use the bit-band alias addresses for this register.
Page 110: C Serial Interface
UG-549 ADuCM310 Hardware Reference Manual C SERIAL INTERFACE C FEATURES The I C interface has the following features: • Master or slave mode with 2-byte transmit and receive FIFOs • Supports • 7-bit and 10-bit addressing modes • Four 7-bit device addresses or one 10-bit address and two 7-bit addresses in the slave •...
Page 111 ADuCM310 Hardware Reference Manual UG-549 Addressing Modes 7-Bit Addressing The I2CxID0, I2CxID1, I2CxID2, and I2CxID3 registers contain the slave device IDs. The device compares the four I2CxIDx registers to the address byte. To be correctly addressed, the seven MSBs of either ID register must be identical to that of the seven MSBs of the first received address byte.
Page 112: I 2 C Operating Modes
UG-549 ADuCM310 Hardware Reference Manual C Clock Control The I C peripherals are clocked by a gated 20 MHz system clock (PCLK). The CLKCON5[3] bit must be cleared to enable the clock to the C0 block. Similarly, the CLKCON5[4] bit must be cleared to enable the clock to the I C1 block.
Page 113 ADuCM310 Hardware Reference Manual UG-549 In the slave, if there is no valid data to transmit when the Tx shifter is loaded, the transmit underflow status bit asserts (I2CxMSTA[12], ISCxSSTA[1]). In slave mode, the Tx FIFO must be loaded with a byte before the falling edge of SCL before the acknowledge/no acknowledge is asserted.
Page 114: Register Summary: I 2 C0
UG-549 ADuCM310 Hardware Reference Manual If the address byte is 0x01, a hardware general call is issued. Byte 2 in this case is the hardware master address. The general call interrupt status bit is set on any general call after the second byte is received, and user code must take corrective action to reprogram the device address.
Page 115: Register Details: I 2 C0
ADuCM310 Hardware Reference Manual UG-549 REGISTER DETAILS: I Master Control Register Address: 0x40003000, Reset: 0x0000, Name: I2CMCON Table 153. Bit Descriptions for I2CMCON Bits Bit Name Description Reset Access [15:12] RESERVED Reserved. MTXDMA Enable master Tx DMA request. 0: disable DMA mode.
Page 116 UG-549 ADuCM310 Hardware Reference Manual Master Status Register Address: 0x40003004, Reset: 0x6000, Name: I2CMSTA Table 154. Bit Descriptions for I2CMSTA Bits Bit Name Description Reset Access RESERVED Reserved. SCL_FILTERED State of SCL line. This bit is the output of the glitch filter on SCL. SCL is always pulled high when undriven.
Page 117 ADuCM310 Hardware Reference Manual UG-549 Master Receive Data Register Address: 0x40003008, Reset: 0x0000, Name: I2CMRX Table 155. Bit Descriptions for I2CMRX Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. [7:0] ICMRX Master receive register. This register allows access to the receive data FIFO.
Page 118 UG-549 ADuCM310 Hardware Reference Manual First Master Address Byte Register Address: 0x40003018, Reset: 0x0000, Name: I2CADR0 Table 159. Bit Descriptions for I2CADR0 Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. [7:0] ADR0 Address Byte 0. If a 7-bit address is required, Bit 7 to Bit 1 of ADR0 are programmed with the address, and Bit 0 of ADR0 is programmed with the direction (0 = write, 1 = read).
Page 119 ADuCM310 Hardware Reference Manual UG-549 Slave Control Register Address: 0x40003028, Reset: 0x0000, Name: I2CSCON Table 162. Bit Descriptions for I2CSCON Bits Bit Name Description Reset Access RESERVED Reserved. STXDMA Enable slave Tx DMA request. Set to 1 by user code to enable I C slave DMA Rx requests.
Page 120 UG-549 ADuCM310 Hardware Reference Manual Slave I C Status/Error/IRQ register Address: 0x4000302C, Reset: 0x0001, Name: I2CSSTA Table 163. Bit Descriptions for I2CSSTA Bits Bit Name Description Reset Access RESERVED Reserved. START Start and matching address. This bit is asserted if a start is detected on SCL/SDA and the device address matched;...
Page 121 ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access STXUR Slave transmit FIFO underflow. This bit is set if a master requests data from the device, and the Tx FIFO is empty for the rising edge of SCL.
Page 122 UG-549 ADuCM310 Hardware Reference Manual Third Slave Address Device ID Register Address: 0x40003044, Reset: 0x0000, Name: I2CID2 Table 169. Bit Descriptions for I2CID2 Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. [7:0] Slave Device ID 2. I2CID2[7:1] is programmed with the device ID. I2CID2[0] is don't care.
Page 123 ADuCM310 Hardware Reference Manual UG-549 Master and Slave Shared Control Register Address: 0x40003050, Reset: 0x0000, Name: I2C0SHCON Table 172. Bit Descriptions for I2C0SHCON Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0000 RESET Write a 1 to this bit to reset the I C start and stop detection circuits.
Page 124: Register Summary: I 2 C1
UG-549 ADuCM310 Hardware Reference Manual REGISTER SUMMARY: I Table 174. I C1 Register Summary Address Name Description Reset Access 0x40003400 I2C1MCON Master control register 0x0000 0x40003404 I2C1MSTA Master status register 0x6000 0x40003408 I2C1MRX Master receive data register 0x0000 0x4000340C I2C1MTX...
Page 125: Register Details: I 2 C1
ADuCM310 Hardware Reference Manual UG-549 REGISTER DETAILS: I Master Control Register Address: 0x40003400, Reset: 0x0000, Name: I2C1MCON Table 175. Bit Descriptions for I2C1MCON Bits Bit Name Description Reset Access [15:12] RESERVED Reserved. MTXDMA Enable master Tx DMA request. 0: disable DMA mode.
Page 126 UG-549 ADuCM310 Hardware Reference Manual Master Status Register Address: 0x40003404, Reset: 0x6000, Name: I2C1MSTA Table 176. Bit Descriptions for I2C1MSTA Bits Bit Name Description Reset Access RESERVED Reserved. SCL_FILTERED State of SCL line. This bit is the output of the glitch filter on SCL. SCL is always pulled high when undriven.
Page 127 ADuCM310 Hardware Reference Manual UG-549 Master Receive Data Register Address: 0x40003408, Reset: 0x0000, Name: I2C1MRX Table 177. Bit Descriptions for I2C1MRX Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. [7:0] ICMRX Master receive register. This register allows access to the receive data FIFO.
Page 128 UG-549 ADuCM310 Hardware Reference Manual First Master Address Byte Register Address: 0x40003418, Reset: 0x0000, Name: I2C1ADR0 Table 181. Bit Descriptions for I2C1ADR0 Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. [7:0] ADR0 Address Byte 0. If a 7-bit address is required, Bit 7 to Bit 1 of ADR0 are programmed with the address and Bit 0 of ADR0 is programmed with the direction (0 = write, 1 = read).
Page 129 ADuCM310 Hardware Reference Manual UG-549 Slave Control Register Address: 0x40003428, Reset: 0x0000, Name: I2C1SCON Table 184. Bit Descriptions for I2C1SCON Bits Bit Name Description Reset Access RESERVED Reserved. STXDMA Enable slave Tx DMA request. Set to 1 by user code to enable I C slave DMA Rx requests.
Page 130 UG-549 ADuCM310 Hardware Reference Manual Slave I C Status/Error/IRQ Register Address: 0x4000342C, Reset: 0x0001, Name: I2C1SSTA Table 185. Bit Descriptions for I2C1SSTA Bits Bit Name Description Reset Access RESERVED Reserved. START Start and matching address. This bit is asserted if a start is detected on SCL/SDA and the device address matched, or a general call (address = 0000_0000) code is received and general call is enabled;...
Page 131 ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access STXUR Slave transmit FIFO underflow. This bit is set if a master requests data from the device, and the Tx FIFO is empty for the rising edge of SCL.
Page 132 UG-549 ADuCM310 Hardware Reference Manual Third Slave Address Device ID Register Address: 0x40003444, Reset: 0x0000, Name: I2C1ID2 Table 191. Bit Descriptions for I2C1ID2 Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. [7:0] Slave device ID 2. I2CID2[7:1] is programmed with the device ID. I2CID2[0] is don't care.
Page 133 ADuCM310 Hardware Reference Manual UG-549 Master and Slave Shared Control Register Address: 0x40003450, Reset: 0x0000, Name: I2C1SHCON Table 194. Bit Descriptions for I2C1SHCON Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0000 RESET Write a 1 to this bit to reset the I C start and stop detection circuits.
Page 134: Serial Peripheral Interfaces
UG-549 ADuCM310 Hardware Reference Manual SERIAL PERIPHERAL INTERFACES SPI FEATURES ADuCM310 integrates two complete hardware serial peripheral interfaces with the following standard SPI features: • Serial clock phase mode and serial clock polarity mode • LSB first transfer option •...
Page 135: Spi Transfer Initiation
ADuCM310 Hardware Reference Manual UG-549 In slave mode, the SPIxCON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master at rates of up to 20 Mbps. In both master and slave modes, data is transmitted on one edge of the SCLK signal and sampled on the other. Therefore, it is important that the polarity and phase be configured the same for the master and slave devices.
Page 136 UG-549 ADuCM310 Hardware Reference Manual CLOCK CYCLE NUMBER SPI CLOCK (CPOL = 0) SPI CLOCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) Figure 24. SPI Transfer Protocol, CPHA = 0 CLOCK CYCLE NUMBER SPI CLOCK (CPOL = 0)
Page 137: Spi Interrupts
ADuCM310 Hardware Reference Manual UG-549 SPI INTERRUPTS There is one interrupt line per SPI and four sources of interrupts. SPIxSTA[0] reflects the state of the interrupt line, and SPIxSTA[7:4] reflects the state of the four sources. The SPI generates either TIRQ or RIRQ. Both interrupts cannot be enabled at the same time. The appropriate interrupt is enabled using the TIM bit, SPIxCON[6].
Page 138: Spi Wire-Or'ed Mode (Wom)
UG-549 ADuCM310 Hardware Reference Manual SPI WIRE-OR’ED MODE (WOM) To prevent contention when the SPI is used in a multimaster or multislave system, the data output pins (MOSI and MISO) can be configured to behave as open-circuit drivers. An external pull-up resistor is required when this feature is selected. The WOM bit (SPIxCON[4]) controls the pad enable outputs for the data lines.
Page 139: Spi And Power-Down Modes
ADuCM310 Hardware Reference Manual UG-549 Performing SPIx DMA Master Receive The DMA SPI Rx channel must be configured. The NVIC must be configured to enable DMA Rx master interrupt (ISER0[29]). The DMA transfer stops when the number of bytes have been transferred. Note that the DMA buffer must be of the same size as SPI1CNT to generate a DMA interrupt when the transfer is complete.
Page 140: Register Summary: Spi0
UG-549 ADuCM310 Hardware Reference Manual REGISTER SUMMARY: SPI0 Table 197. SPI0 Register Summary Address Name Description Reset Access 0x4002C000 SPI0STA Status register 0x0000 0x4002C004 SPI0RX Receive register 0x0000 0x4002C008 SPI0TX Transmit register 0x0000 0x4002C00C SPI0DIV Baud rate selection register 0x0000...
Page 141: Changes To Table 201
ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access SPI Tx IRQ status bit. Not available in DMA mode. 0: CLR. Cleared to 0 when the SPI0STA register is read. 1: SET. Set to 1 when a transmit interrupt occurs. This bit is set when TIM in SPI0CON is set and the required number of bytes have been transmitted.
Page 142 UG-549 ADuCM310 Hardware Reference Manual Bits Bit Name Description Reset Access High frequency mode. This bit is used for applications using high frequency where the pad introduces a significant delay on the SCL. This can cause a significant enough difference between the serial clock and the data being received on the Rx shift register.
Page 143 ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access SPI transfer and interrupt mode. 0: cleared by user to initiate transfer with a read of the SPI0RX register. Interrupt only occurs when Rx is full. 1: set by user to initiate transfer with a write to the SPI0TX register.
Page 144: Register Summary: Spi1
UG-549 ADuCM310 Hardware Reference Manual REGISTER SUMMARY: SPI1 Table 205. SPI1 Register Summary Address Name Description Reset Access 0x40030000 SPI1STA Status register 0x0000 0x40030004 SPI1RX Receive register 0x0000 0x40030008 SPI1TX Transmit register 0x0000 0x4003000C SPI1DIV Baud rate selection register 0x0000...
Page 145 ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access SPI Tx IRQ. Status bit. Not available in DMA mode. 0: CLR. Cleared to 0 when the SPI1STA register is read. 1: SET. Set to 1 when a transmit interrupt occurs. This bit is set when TIM in SPI1CON is set and the required number of bytes have been transmitted.
Page 146 UG-549 ADuCM310 Hardware Reference Manual Bits Bit Name Description Reset Access High frequency mode. This bit is used for applications using high frequency where the pad introduces a significant delay on the SCL, which can cause a significant enough difference between the serial clock and the data being received on the Rx shift register.
Page 147 ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access SPI transfer and interrupt mode. 0: cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full. 1: set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty.
Page 148: Uart Serial Interface
UG-549 ADuCM310 Hardware Reference Manual UART SERIAL INTERFACE UART FEATURES ADuCM310 features an industry standard, 16450 UART peripheral with support for DMA. UART OVERVIEW The UART peripheral is a full-duplex universal asynchronous receiver/transmitter (UART), compatible with the industry standard, 16450.
Page 149 ADuCM310 Hardware Reference Manual UG-549 Programmed Input/Output Mode In programmed input/output mode, the software is responsible for moving data to and from the UART. This is typically accomplished by interrupt service routines that respond to the transmit and receive interrupts by either reading or writing data as appropriate. This mode places certain constraints on the software itself in that the software must respond within a certain time to prevent overflow errors from occurring in the receive channel.
Page 150 UG-549 ADuCM310 Hardware Reference Manual Example Code to Set Up UART Receive DMA Channel void UARTRXDMAINIT(void) NVIC_EnableIRQ(DMA_UART_RX_IRQn); // UArt Tx DMA interrupt enable pADI_UART->COMLCR = COMLCR_WLS_EIGHTBITS | COMLCR_STOP; // 8-data bits + 1 Stop bit. pADI_UART->COMDIV = 0x41; // Set UART Baud rate pADI_UART->COMFBR = COMFBR_FBEN_EN | 0x803;...
Page 151 ADuCM310 Hardware Reference Manual UG-549 Example Code to Set Up UART Transmit DMA Channel void UARTTXDMAINIT(void) NVIC_EnableIRQ(DMA_UART_TX_IRQn); // UART Tx DMA interrupt sources pADI_UART->COMLCR = COMLCR_WLS_8BITS + COMLCR_STOP; // 8-data bits + 1 Stop bit. pADI_UART->COMDIV = 0x41; // Set UART Baud rate pADI_UART->COMFBR = COMFBR_FBEN_EN | 0x803;...
Page 152: Register Summary: Uart
UG-549 ADuCM310 Hardware Reference Manual REGISTER SUMMARY: UART Table 213. UART Register Summary Address Name Description Reset Access 0x40005000 COMTX Transmit holding register 0x0000 0x40005000 COMRX Receive buffer register 0x0000 0x40005004 COMIEN Interrupt enable register 0x0000 0x40005008 COMIIR Interrupt identification register...
Page 153 ADuCM310 Hardware Reference Manual UG-549 Interrupt Enable Register Address: 0x40005004, Reset: 0x0000, Name: COMIEN COMIEN is the interrupt enable register that configures which interrupt source generates the interrupt. Only the lowest four bits in this register enable interrupts. Bit 4 and Bit 5 enable UART DMA signals. The UART DMA channel and interrupt must be configured in the DMA block.
Page 154 UG-549 ADuCM310 Hardware Reference Manual Bits Bit Name Description Reset Access Stick parity. Forces parity to defined values. When set, the parity is based on the following bit settings: EPS = 1 and PEN = 1, parity is forced to 0.
Page 155 ADuCM310 Hardware Reference Manual UG-549 Line Status Register Address: 0x40005014, Reset: 0x0060, Name: COMLSR Table 220. Bit Descriptions for COMLSR Bits Bit Name Description Reset Access [15:7] RESERVED Reserved. TEMT COMTX and shift register empty status. 0: COMTX has been written to and contains data to be transmitted. Take care not to overwrite its value.
Page 156 UG-549 ADuCM310 Hardware Reference Manual Bits Bit Name Description Reset Access TERI Trailing edge RI. If set, this bit self clears after COMMSR is read. 0: RI has not changed from 0 to 1 since COMMSR was last read. 1: RI changed from 0 to 1 since COMMSR was last read.
Page 157: General-Purpose Timers
ADuCM310 Hardware Reference Manual UG-549 GENERAL-PURPOSE TIMERS GENERAL-PURPOSE TIMERS FEATURES ADuCM310 integrates three general-purpose timers with the following features: • Three identical, general-purpose, 16-bit count-up/count-down timers • Timer 0, Timer 1, and Timer 2 • Clocked from four different clocks •...
Page 158: General-Purpose Timers Operation
UG-549 ADuCM310 Hardware Reference Manual An interrupt signal is generated each time the value of the counter reaches zero when counting down, or each time the counter value reaches the maximum value when counting up. An IRQ can be cleared by writing 1 to the time clear interrupt register of that particular timer (TxCLRI).
Page 159 ADuCM310 Hardware Reference Manual UG-549 Capture Event Function There are a number of interrupt events that can be captured by the general-purpose timers. These events are shown in Table 225. Any of the events associated with a general-purpose timer can cause a capture of the 16-bit TxVAL register into the 16-bit TxCAP register.
Page 160: Register Summary: General-Purpose Timer 0
UG-549 ADuCM310 Hardware Reference Manual REGISTER SUMMARY: GENERAL-PURPOSE TIMER 0 Table 226. Timer 0 Register Summary Address Name Description Reset Access 0x40000000 T0LD 16-bit load value register 0x0000 0x40000004 T0VAL 16-bit timer value register 0x0000 0x40000008 T0CON Control register 0x000A...
Page 161 ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access ENABLE Timer enable. This bit enables and disables the timer. Clearing this bit resets the timer, including the T0VAL register. 0: DIS. Timer is disabled (default). 1: EN. Timer is enabled.
Page 162 UG-549 ADuCM310 Hardware Reference Manual Status Register Address: 0x4000001C, Reset: 0x0000, Name: T0STA Table 232. Bit Descriptions for T0STA Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. PDOK T0CLRI synchronization. This bit is set automatically when the user sets T0CLRI[0] = 1.
Page 163: Register Summary: General-Purpose Timer 1
ADuCM310 Hardware Reference Manual UG-549 REGISTER SUMMARY: GENERAL-PURPOSE TIMER 1 Table 233. Timer 1 Register Summary Address Name Description Reset Access 0x40000400 T1LD 16-bit load value register 0x0000 0x40000404 T1VAL 16-bit timer value register 0x0000 0x40000408 T1CON Control register 0x000A...
Page 164 UG-549 ADuCM310 Hardware Reference Manual Bits Bit Name Description Reset Access ENABLE Timer enable. This bit enables and disables the timer. Clearing this bit resets the timer, including the T1VAL register. 0: DIS. Timer is disabled (default). 1: EN. Timer is enabled.
Page 165 ADuCM310 Hardware Reference Manual UG-549 Status Register Address: 0x4000041C, Reset: 0x0000, Name: T1STA Table 239. Bit Descriptions for T1STA Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. PDOK T1CLRI synchronization. This bit is set automatically when the user sets T1CLRI[0] = 1.
Page 166: Register Summary: General-Purpose Timer 2
UG-549 ADuCM310 Hardware Reference Manual REGISTER SUMMARY: GENERAL-PURPOSE TIMER 2 Table 240. Timer 2 Register Summary Address Name Description Reset 0x40000800 T2LD 16-bit load value register 0x0000 0x40000804 T2VAL 16-bit timer value register 0x0000 0x40000808 T2CON Control register 0x000A 0x4000080C...
Page 167 ADuCM310 Hardware Reference Manual UG-549 Bits Bit Name Description Reset Access ENABLE Timer enable. This bit enables and disables the timer. Clearing this bit resets the timer, including the T2VAL register. 0: DIS. Timer is disabled (default). 1: EN. Timer is enabled.
Page 168 UG-549 ADuCM310 Hardware Reference Manual Status Register Address: 0x4000081C, Reset: 0x0000, Name: T2STA Table 246. Bit Descriptions for T2STA Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. PDOK T2CLRI synchronization. This bit is set automatically when the user sets T2CLRI[0] = 1.
Page 169: Watchdog Timer
ADuCM310 Hardware Reference Manual UG-549 WATCHDOG TIMER WATCHDOG TIMER FEATURES The watchdog timer is a 16-bit count-down timer, which can recover from an invalid software state. The watchdog timer is clocked by the 32 kHz internal oscillator (LFOSC) with a programmable prescaler (1, 16,256, or 4096).
Page 170: Register Details: Watchdog Timer
UG-549 ADuCM310 Hardware Reference Manual REGISTER DETAILS: WATCHDOG TIMER Load Value Register Address: 0x40002580, Reset: 0x1000, Name: T3LD Table 248. Bit Descriptions for T3LD Bits Bit Name Description Reset Access [15:0] LOAD Load value 0x1000 Current Count Value Register Address: 0x40002584, Reset: 0x1000, Name: T3VAL Table 249.
Page 171 ADuCM310 Hardware Reference Manual UG-549 Clear Interrupt Register Address: 0x4000258C, Reset: 0x0000, Name: T3CLRI Table 251. Bit Descriptions for T3CLRI Bits Bit Name Description Reset Access [15:0] CLRWDG Clear watchdog. User writes 0xCCCC to reset/reload/restart Timer 3 or clear IRQ. A write of any other value causes a watchdog reset. This register is write only;...
Page 172: Wake-Up Timer
UG-549 ADuCM310 Hardware Reference Manual WAKE-UP TIMER WAKE-UP TIMER FEATURES The wake-up timer has the following features: • 32-bit counter (count down or count up) • Four clock sources with programmable prescaler (1, 16,256, or 32,768) • Peripheral clock (PCLK) •...
Page 173 ADuCM310 Hardware Reference Manual UG-549 Compare Field Registers Hardware Updated Field T4INC is a 12-bit interval register that updates the compare value in T4WUFAx by hardware. When a new value is written in T4INC, Bits[16:5] of the internal 32-bit compare register (T4WUFAx) are loaded with the new T4INC value. If the new compare value is less than the T4WUFD value in periodic mode or less than 0xFFFFFFFF in free running mode, this 32-bit compare register is automatically incremented with the contents of T4INC (shifted by five) each time the wake-up counter reaches the value in this compare register.
Page 174: Register Summary: Wake-Up Timer
UG-549 ADuCM310 Hardware Reference Manual Interrupts/Wake-Up Signals An interrupt is generated when the counter value corresponds to any of the compare points or full scale in free running mode. The timer continues counting or is reset to zero. The wake-up timer generates five maskable interrupts. They are enabled in the T4IEN register. Interrupts can be cleared by setting the corresponding bit in the T4CLRI register.
Page 175 ADuCM310 Hardware Reference Manual UG-549 Control Register Address: 0x40002508, Reset: 0x0040, Name: T4CON Table 256. Bit Descriptions for T4CON Bits Bit Name Description Reset Access [15:12] RESERVED Reserved. STOP_WUFA Disables updating Field A register T4WUFA. When set, this bit stops the Wake-Up Field A register T4WUFA from being updated with the interval register I2INC value.
Page 176 UG-549 ADuCM310 Hardware Reference Manual Wake-Up Field B—Most Significant 16 Bits Register Address: 0x40002514, Reset: 0x0000, Name: T4WUFB1 Table 259. Bit Descriptions for T4WUFB1 Bits Bit Name Description Reset Access [15:0] T4WUFBH Wake-Up Field B High. Most significant 16 bits of Wake-Up Field B.
Page 177 ADuCM310 Hardware Reference Manual UG-549 Status Register Address: 0x4000252C, Reset: 0x0000, Name: T4STA Table 265. Bit Descriptions for T4STA Bits Bit Name Description Reset Access [15:9] RESERVED Reserved. PDOK Enable bit synchronized. Indicates when a change in the enable bit is synchronized to the 32 kHz clock domain.
Page 178: Pulse Width Modulation (Pwm)
UG-549 ADuCM310 Hardware Reference Manual PULSE WIDTH MODULATION (PWM) PWM FEATURES ADuCM310 features an 8-channel PWM interface. PWM OVERVIEW ADuCM310 integrates an 8-channel PWM interface. Eight channels are grouped as four pairs (0 to 3). The first two pairs of PWM outputs (PWM0 PWM1, PWM2, and PWM3) can be configured to drive an H-bridge.
Page 179 ADuCM310 Hardware Reference Manual UG-549 Table 270 lists equations for the period and duration for both the outputs of a PWM channel. Note that t is the PWM clock UCLK/DIV frequency selected by CLKCON1[2:0] and CLKSYSDIV[0], and N is the prescalar value as determined by PWMCON0[8:6].
Page 180: Pwm Interrupt Generation
UG-549 ADuCM310 Hardware Reference Manual H-Bridge Mode In H-bridge mode, the two pairs of frequency and duty cycle are controlled by PWM0COM0, PWM0COM1, and PWM0LEN. For H-bridge mode, HMODE = 1 (PWMCON0[1] = 1). The HMODE bit also works with PWMCON0[5:2] for H-bridge mode. Note that only PWM0 to PWM3 participate in H-bridge mode;...
Page 181: Register Summary: Pwm
ADuCM310 Hardware Reference Manual UG-549 REGISTER SUMMARY: PWM Table 273. PWM Register Summary Address Name Description Reset Access 0x40024000 PWMCON0 PWM control register 0x0012 0x40024004 PWMCON1 ADC conversion start and trip control register 0x0000 0x40024008 PWMICLR Hardware trip configuration register...
Page 182 UG-549 ADuCM310 Hardware Reference Manual Bits Bit Name Description Reset Access LCOMP Signal to load a new set of compare register values. In standard mode, this bit is cleared when the new values are loaded in the compare registers for all the channels.
Page 183 ADuCM310 Hardware Reference Manual UG-549 Compare Register 0 for PWM2 and PWM3 Address: 0x40024020, Reset: 0x0000, Name: PWM1COM0 Table 279. Bit Descriptions for PWM1COM0 Bits Bit Name Description Reset Access [15:0] COM0 Compare Register 0 data Compare Register 1 for PWM2 and PWM3 Address: 0x40024024, Reset: 0x0000, Name: PWM1COM1 Table 280.
Page 184 UG-549 ADuCM310 Hardware Reference Manual Compare Register 0 for PWM6 and PWM7 Address: 0x40024040, Reset: 0x0000, Name: PWM3COM0 Table 287. Bit Descriptions for PWM3COM0 Bits Bit Name Description Reset Access [15:0] COM0 Compare Register 0 data Compare Register 1 for PWM6 and PWM7 Address: 0x40024044, Reset: 0x0000, Name: PWM3COM1 Table 288.
Page 185: Programmable Logic Array (Pla)
ADuCM310 Hardware Reference Manual UG-549 PROGRAMMABLE LOGIC ARRAY (PLA) PLA FEATURES ADuCM310 integrates a fully programmable logic array (PLA) that consists of four independent but interconnected PLA blocks. Each block consists of eight PLA elements: Block x Element 0 to Block x Element 7, where x is the block number. Each ADuCM310 4 blocks, giving a total of 32 PLA elements: Element 0 to Element 31.
Page 186: Pla Operation
UG-549 ADuCM310 Hardware Reference Manual In total, 27 GPIO pins are available on each ADuCM310 for the PLA. These include 14 input pins and 13 output pins, which must be configured in the GPxCON register as PLA pins before using the PLA.
Page 187 ADuCM310 Hardware Reference Manual UG-549 BLOCK 2 OUTPUT ELEMENT (n – 16) BLOCK 0 BLOCK 2 ELEMENT 0 (ELEMENT 16) BLOCK 0 ELEMENT 0 (ELEMENT 0) OUTPUT OUTPUT BLOCK 2 ELEMENT 7 BLOCK 0 ELEMENT 7 (ELEMENT 23) (ELEMENT 7)
Page 188 UG-549 ADuCM310 Hardware Reference Manual Table 291. Element GPIO Input/Output PLA Block 0 PLA Block 1 PLA Block 2 PLA Block 3 Element Input Output Element Input Output Element Output Element Output P0.0 P2.0 P0.1 P2.1 P0.2 P0.4 P2.2 P1.4 P2.4...
Page 189: Register Summary: Pla
ADuCM310 Hardware Reference Manual UG-549 REGISTER SUMMARY: PLA Table 295. PLA Register Summary Address Name Description Reset Access 0x40005800 PLA_ELEMn ELEMx configuration register 0x0000 0x40005880 PLA_CLK PLA clock select 0x0000 0x40005884 PLA_IRQ0 Interrupt register for Block 0 and Block 1...
Page 190 UG-549 ADuCM310 Hardware Reference Manual Bits Bit Name Description Reset Access MUX4 Select or bypass flip-flop output. 0: flip-flop output. 1: bypass output PLA Clock Select Register Address: 0x40005880, Reset: 0x0000, Name: PLA_CLK Table 297. Bit Descriptions for PLA_CLK Bits...
Page 191 ADuCM310 Hardware Reference Manual UG-549 Interrupt Register for Block 0 and Block 1 Address: 0x40005884, Reset: 0x0000, Name: PLA_IRQ0 Table 298. Bit Descriptions for PLA_IRQ0 Bits Bit Name Description Reset Access [15:13] RESERVED Not used. Reserved IRQ1_EN IRQ1 enable. 0: disable IRQ1 interrupt.
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