Changes To Table 17 - Analog Devices ADuCM320 Hardware Reference Manual

UG-498
ADC Sequencer Configuration Register
Address: 0x4008608C, Reset: 0x0008C631, Name: ADCSEQC
Table 17. Bit Descriptions for ADCSEQC
Bits Bit Name Description
[31:28] RESERVED Reserved.
[27:20] T Define programmable delay of 0 to 254 between sequences. A delay of 255 causes a
halt after one sequence. Set ADCSEQ[30] if another sequence is required.
[19:15] DIF6 Selects differential mode negative input for AIN6 in the sequence. See ADCCHA[12:8]
for list of channels.
0x11: Channel 6 is single ended
[14:10] DIF4 Selects differential mode negative input for AIN4 in the sequence. See ADCCHA[12:8]
for list of channels.
0x11: Channel 4 is single ended
[9:5] DIF2 Selects differential mode negative input for AIN2 in the sequence. See ADCCHA[12:8]
for list of channels.
0x11: Channel 2 is single ended
[4:0] DIF0 Selects differential mode negative input for AIN0 in the sequence. See ADCCHA[12:8]
for list of channels.
0x11: Channel 0 is single ended
Digital Comparator Configuration Register
Address: 0x40086098, Reset: 0x00000, Name: ADCCMP
Table 18. Bit Descriptions for ADCCMP
Bits Bit Name Description
[17:2] THR Digital compare threshold. Value to compare to Channel 4 data.
1 DIR Select digital comparator direction.
0: ADCTH less than Channel 4 data
1: ADCTH larger than Channel 4 data
0 EN Digital comparator enable.
0: Disable
1: Enable
ADC Conversion Configuration Register
Address: 0x4008609C, Reset: 0x000A00C8, Name: ADCCNVC
Note that, when ADCCP is set to 22 (temp sensor) or 25 (IOVDD/2) or 26 (AVDD/2), the ADCCNVC register automatically changes to
0x7D00FA − (80 kSPS) for single conversions. ADCCNVC should be set to the required conversion rate after sampling these 3× channels
if a different sample rate is required for other ADC input channels.
Note that, when the sequencer is enabled and includes any of these 3× channels, the value in ADCCNVC does not change and the ADC
sampling rate does not change.
Table 19. Bit Descriptions for ADCCNVC
Bits Bit Name Description
[31:26] RESERVED Do not overwrite
[25:16] CNVD Configure ADC acquisition time and sampling time
Acquisition time = CNVD/20 MHz
Default acquisition time is 500 ns
For best SNR results, ensure that the acquisition time is set to ≥500 ns for all ADC
conversion rates
[15:10] RESERVED Do not overwrite
[9:0] CNVC Configure conversion frequency.
Conversion frequency = 20 MHz/CNVC
ADuCM320 Hardware Reference Manual
Rev. C | Page 32 of 196
Reset Access
0x0 R
0x0 RW
0x11 RW
0x11 RW
0x11 RW
0x11 RW
Reset Access
0x0000 RW
0x0 RW
0x0 RW
Reset Access
0x0 RW
0xA RW
0x00 RW
0xC8 RW