Arm Cortex-M3 Processor Related Documents - Analog Devices ADuCM320 Hardware Reference Manual

UG-498
Nested Vectored Interrupt Controller Interrupts (NVIC)
The ARM Cortex-M3 processor includes a nested vectored interrupt controller (NVIC), which offers several features:
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Nested interrupt support
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Vectored interrupt support
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Dynamic priority changes support
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Interrupt masking
In addition, the NVIC has a nonmaskable interrupt (NMI) input.
The NVIC is implemented on the ADuCM320, and more details are available in the System Exceptions and Peripheral Interrupts section.
Wake-Up Interrupt Controller (WIC)
The ADuCM320 has a modified WIC, which provides the lowest possible power-down current. This feature is transparent to the user and
more details are available in the Power Management Unit section. It is not recommended to enter a power saving mode while servicing an
interrupt. However, if the part does enter a power saving mode while servicing an interrupt, it can be woken up by only a higher priority
interrupt source.
μDMA
The ADuCM320 implements the ARM μDMA. More details are available in the DMA Controller section.

ARM CORTEX-M3 PROCESSOR RELATED DOCUMENTS

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Cortex-M3 Revision r2p1 Technical Reference Manual (DDI 0337)
•
ARM Processor Cortex-M3 (AT420) and Cortex-M3 with ETM AT425): Errata Notice
•
ARMv7-M Architecture Reference Manual (DDI 0403)
•
ARMv7-M Architecture Reference Manual Errata Markup
•
ARM Debug Interface v5 Architecture Specification (IHI 0031)
•
PrimeCell µDMA Controller (PL230) Technical Reference Manual Revision r0p0 (DDI 0417)
ADuCM320 Hardware Reference Manual
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