Register Summary: Watchdog Timer; Register Details: Watchdog Timer - Analog Devices ADuCM320 Hardware Reference Manual

ADuCM320 Hardware Reference Manual

REGISTER SUMMARY: WATCHDOG TIMER

Table 242. Watchdog Timer Register Summary
Address
0x40002580
0x40002584
0x40002588
0x4000258C
0x40002598

REGISTER DETAILS: WATCHDOG TIMER

Load Value Register
Address: 0x40002580, Reset: 0x1000, Name: T3LD
Table 243. Bit Descriptions for T3LD
Bits Bit Name
[15:0] LOAD
Current Count Value Register
Address: 0x40002584, Reset: 0x1000, Name: T3VAL
Table 244. Bit Descriptions for T3VAL
Bits Bit Name
[15:0] CCOUNT
Control Register
Address: 0x40002588, Reset: 0x00E9, Name: T3CON
Table 245. Bit Descriptions for T3CON
Bits Bit Name Description
[15:7] RESERVED Reserved.
6 MOD Timer mode. Note that in free running mode it wraps around at 0x1000.
0: FREERUN. Cleared by user to operate in free running mode.
1: PERIODIC. Set by user to operate in periodic mode (default).
5 ENABLE Timer enable.
0: DIS. Cleared by user to disable the timer.
1: EN. Set by user to enable the timer (default).
4 RESERVED Reserved.
[3:2] PRE Prescaler.
00: DIV1. Source clock/1.
01: DIV16. Source clock/16.
10: DIV256. Source clock/256 (default).
11: DIV4096. Source clock/4096
1 IRQ Timer interrupt.
0: DIS. Cleared by user to generate a reset on a time out (default).
1: EN. Set by user to generate an interrupt when the timer times out. This feature is provided for
debug purposes and is only available in active mode.
0 PMD Power Mode Disable. PMD controls the behavior of the watchdog when in hibernate mode. If the
application requires prolonged periods of time spent in hibernate mode and it is not desirable to
periodically wake up to service the watchdog timer, the counter within the watchdog timer can be
suspended when entering the hibernate power mode. Regardless of how the PMD bit is set, it is
recommended that the watchdog timer be cleared before entering hibernate mode.
0: DIS. The watchdog timer continues its countdown while in hibernate mode.
1: EN. When hibernate mode is entered, the watchdog counter suspends its countdown. When
hibernate mode is exited, the countdown resumes from its current count value (the count is not reset).
Name Description
T3LD Load value register
T3VAL Current count value register
T3CON Control register
T3CLRI Clear interrupt register
T3STA Status register
Description
Load value
Description
Current count value.
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UG-498
Reset RW
0x1000 RW
0x1000 R
0x00E9 RW
0x0000 W
0x0000 R
Reset Access
0x1000 RW
Reset Access
0x1000 R
Reset Access
0x1 R
0x1 RW
0x1 RW
0x0 R
0x2 RW
0x0 RW
0x1 RW