Analog Devices ADuCM320 Hardware Reference Manual page 173

ADuCM320 Hardware Reference Manual
Bits Bit Name
7 ENABLE
6 MOD
[5:4] RESERVED
3 FREEZE
2 RESERVED
[1:0] PRE
12-Bit Interval for Wake-Up Field A Register
Address: 0x4000250C, Reset: 0x00C8, Name: T4INC
Table 252. Bit Descriptions for T4INC
Bits Bit Name
[15:12] RESERVED
[11:0] INTERVAL
Wake-Up Field B—Least Significant 16 Bits Register
Address: 0x40002510, Reset: 0x1FFF, Name: T4WUFB0
Table 253. Bit Descriptions for T4WUFB0
Bits Bit Name
[15:0] T4WUFBL
Wake-Up Field B—Most Significant 16 Bits Register
Address: 0x40002514, Reset: 0x0000, Name: T4WUFB1
Table 254. Bit Descriptions for T4WUFB1
Bits Bit Name
[15:0] T4WUFBH
Wake-Up Field C—Least Significant 16 Bits Register
Address: 0x40002518, Reset: 0x2FFF, Name: T4WUFC0
Table 255. Bit Descriptions for T4WUFC0
Bits Bit Name
[15:0] T4WUFCL
Description
Timer enable.
0: DIS: disable the timer (default)
1: EN: enable the timer
Timer mode.
0: PERIODIC: cleared by user to operate in periodic mode. In this mode, the
timer counts up to T4WUFD.
1: FREERUN: set by user to operate in free running mode (default).
Reserved. These bits should be written 0.
Freeze enable.
0: DIS: Cleared by user to disable this feature (default).
1: EN: Set by user to enable the freeze of the high 16-bits after the lower
bits have been read from T4VAL0. This ensures that the software reads an
atomic shot of the timer. T4VAL1 unfreezes after it has been read.
Reserved.
Prescaler.
00: PREDIV1: source clock/1 (default). If the selected clock source is PCLK,
this setting results in a prescaler of 4.
01: PREDIV16: source clock/16
10: PREDIV256: source clock/256
11: PREDIV32768: source clock/32,768
Description
Reserved.
Interval for Wake-Up Field A.
Description
Wake-Up Field B low. Least significant 16 bits of Wake-Up Field B.
Description
Wake-Up Field B High. Most significant 16 bits of Wake-Up Field B.
Description
Wake-Up Field C Low. Least significant 16 bits of Wake-Up Field C.
Rev. C | Page 173 of 196
UG-498
Reset Access
0x0 RW
0x1 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x0C8 RW
Reset Access
0x1FFF RW
Reset Access
0x0 RW
Reset Access
0x2FFF RW