Analog Devices ADuCM320 Hardware Reference Manual page 52

UG-498
Table 55. NVIC Registers
Address Analog Devices Header File Name
0xE000E004 ICTR
0xE000E010 STCSR
0xE000E014 STRVR
0xE000E018 STCVR
0xE000E01C STCR
0xE000E100 ISER0
0xE000E104 ISER1
0xE000E180 ICER0
0xE000E184 ICER1
0xE000E200 ISPR0
0xE000E204 ISPR1
0xE000E280 ICPR0
0xE000E284 ICPR1
0xE000E300 IABR0
0xE000E304 IABR1
0xE000E400 IPR0
0xE000E404 IPR1
0xE000E408 IPR2
0xE000E40C IPR3
0xE000E410 IPR4
0xE000E414 IPR5
0xE000E418 IPR6
0xE000E41C IPR7
0xE000E420 IPR8
0xE000E424 IPR9
0xE000E428 IPR10
0xE000E42C IPR11
0xE000E430 IPR12
0xE000E434 IPR13
0xE000ED00 CPUID
0xE000ED04 ICSR
0xE000ED08 VTOR
0xE000ED0C AIRCR
0xE000ED10 SCR
0xE000ED14 CCR
0xE000ED18 SHPR1
0xE000ED1C SHPR2
0xE000ED20 SHPR3
0xE000ED24 SHCRS
0xE000ED28 CFSR
0xE000ED2C HFSR
0xE000ED34 MMAR
0xE000ED38 BFAR
0xE000EF00 STIR
ADuCM320 Hardware Reference Manual
Description
Shows the number of interrupt lines that the NVIC supports.
SYSTICK control and status register.
SYSTICK reload value register.
SYSTICK current value register.
SYSTICK calibration value register.
Set IRQ0 to IRQ31 enable. Each bit corresponds to Interrupt 0 to
Interrupt 31 in Table 54.
Set IRQ32 to IRQ54 enable. Each bit corresponds to interrupt 32 to
Interrupt 54 in Table 54.
Clear IRQ0 to IRQ31 by setting appropriate bit. Each bit corresponds to
Interrupt 0 to Interrupt 31 in Table 54.
Clear IRQ32 to IRQ54 by setting appropriate bit. Each bit corresponds to
Interrupt 32 to Interrupt 54 in Table 54.
Set IRQ0 to IRQ31 pending. Each bit corresponds to Interrupt 32 to
Interrupt 38 in Table 54.
Set IRQ32 to IRQ54 pending. Each bit corresponds to Interrupt 32 to
Interrupt 54 in Table 54.
Clear IRQ0 to IRQ31 pending. Each bit corresponds to Interrupt 32 to
Interrupt 38 in Table 54.
Clear IRQ32 to IRQ54 pending. Each bit corresponds to Interrupt 32 to
Interrupt 54 in Table 54.
IRQ0 to IRQ31 active bits.
IRQ32 to IRQ54 active bits.
IRQ0 to IRQ3 priority.
IRQ4 to IRQ7 priority.
IRQ8 to IRQ11 priority.
IRQ12 to IRQ15 priority.
IRQ16 to IRQ19 priority.
IRQ20 to IRQ23 priority.
IRQ24 to IRQ27 priority.
IRQ28 to IRQ31 priority.
IRQ32 to IRQ35 priority.
IRQ36 to IRQ39 priority.
IRQ40 to IRQ43 priority.
IRQ44 to IRQ47 priority.
IRQ48 to IRQ51 priority.
IRQ52 to IRQ54 priority.
CPUID base register.
Interrupt control and status register.
Vector table offset register.
Application interrupt/reset control register.
System control register.
Configuration control register.
System Handlers Register 1.
System Handlers Register 2.
System Handlers Register 3.
System handler control and state.
Configurable fault status.
Hard fault status.
Memory manage fault address register.
Bus fault address.
Software trigger interrupt register.
Rev. C | Page 52 of 196
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