Changes To Protection, Integrity Section - Analog Devices ADuCM320 Hardware Reference Manual

UG-498
DMA Channel Bytes Swap Enable Set Register
Address: 0x40010800, Reset: 0x00000000, Name: DMABSSET
Table 92. Bit Descriptions for DMABSSET
Bits Bit Name
[31:14] RESERVED
[13:0] CHBSWAPSET
DMA Channel Bytes Swap Enable Clear Register
Address: 0x40010804, Reset: 0x00000000, Name: DMABSCLR
Table 93. Bit Descriptions for DMABSCLR
Bits Bit Name
[31:14] RESERVED
[13:0] CHBSWAPCLR
Description
Reserved. Undefined.
Byte swap status. This register is used to configure a DMA channel to use byte. Each
bit of the register represents the corresponding channel number in the DMA
controller.
Bit 0 corresponds to DMA Channel 0, and Bit M-1 corresponds to DMA Channel M-1.
When read:
Bit [C] = 0, Channel C byte swap is disabled.
Bit [C] = 1, Channel C byte swap is enabled.
When written:
Bit [C] = 0, no effect. Use the DMABSCLR register to disable byte swap on Channel C.
Bit [C] = 1, enables byte swap on Channel C.
Description
Reserved. Undefined.
Disable byte swap. The DMABSCLR write-only register enables the user to configure a
DMA channel to not use byte swapping and use the default operation. Each bit of the
register represents the corresponding channel number in the DMA controller.
Bit 0 corresponds to DMA Channel 0, and Bit M-1 corresponds to DMA Channel M-1.
When written:
Bit [C] = 0, no effect. Use the DMABSSET register to enable byte swap on Channel C.
Bit [C] = 1, disables byte swap on Channel C.
ADuCM320 Hardware Reference Manual
Rev. C | Page 72 of 196
Reset Access
0x0 R
0x0 RW
Reset Access
0x0 R
0x0 W