Analog Devices ADuCM320 Hardware Reference Manual page 131

ADuCM320 Hardware Reference Manual
Bits Bit Name
10 LOOPBACK
9 OEN
8 RXOF
7 ZEN
6 TIM
5 LSB
4 WOM
3 CPOL
2 CPHA
1 MASEN
0 ENABLE
Description
Loopback enable.
0: cleared by user to be in normal mode.
1: set by user to connect MISO to MOSI and test software.
Slave MISO output enable.
0: clear this bit to disable the output driver on the MISO pin. The MISO pin
is open-circuit when this bit is clear.
1: set this bit for MISO to operate as normal.
SPIRX overflow overwrite enable.
0: cleared by user, the new serial byte received is discarded.
1: set by user, the valid data in the Rx register is overwritten by the new
serial byte received.
Transmit zeros enable.
0: clear this bit to transmit the last transmitted value when there is no valid
data in the Tx FIFO.
1: set this bit to transmit "0x00" when there is no valid data in the Tx FIFO.
SPI transfer and interrupt mode.
0: cleared by user to initiate transfer with a read of the SPI0RX register.
Interrupt only occurs when Rx is full.
1: set by user to initiate transfer with a write to the SPI0TX register.
Interrupt only occurs when Tx is empty.
LSB first transfer enable.
0: MSB transmitted first
1: LSB transmitted first
SPI wired Or mode.
1: enables open circuit data output enable. External pull-ups required on
data out pins.
0: normal output levels.
Serial clock polarity.
0: serial clock idles low
1: serial clock idles high
Serial clock phase mode.
1: serial clock pulses at the beginning of each serial bit transfer
0: serial clock pulses at the end of each serial bit transfer
Master mode enable.
0: enable slave mode
1: enable master mode
SPI enable.
0: disable the SPI
1: enable the SPI
Rev. C | Page 131 of 196
UG-498
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW