Analog Devices ADuCM320 Hardware Reference Manual page 181

ADuCM320 Hardware Reference Manual
Bits Bit Name
3 LCOMP
2 DIR
1 HMODE
0 PWMEN
ADC Conversion Start And Trip Control Register
Address: 0x40024004, Reset: 0x0000, Name: PWMCON1
Table 270. Bit Descriptions for PWMCON1
Bits Bit Name
[15:7] RESERVED
6 TRIP_EN
[5:0] RESERVED
Hardware Trip Configuration Register
Address: 0x40024008, Reset: 0x0000, Name: PWMICLR
Table 271. Bit Descriptions for PWMICLR
Bits Bit Name
[15:5] RESERVED
4 TRIP
3 PWM3
2 PWM2
1 PWM1
0 PWM0
Compare Register 0 for PWM0 and PWM1
Address: 0x40024010, Reset: 0x0000, Name: PWM0COM0
Table 272. Bit Descriptions for PWM0COM0
Bits Bit Name
[15:0] COM0
Compare Register 1 for PWM0 and PWM1
Address: 0x40024014, Reset: 0x0000, Name: PWM0COM1
Table 273. Bit Descriptions for PWM0COM1
Bits Bit Name
[15:0] COM1
Description
Signal to load a new set of compare register values. In standard mode, this
bit is cleared when the new values are loaded in the compare registers for
all the channels. In H-bridge mode, this bit is not cleared; however, the
user must write a value of 1 to this bit for the compare registers to be loaded.
0: use the values previously store in the compare and length registers
1: load the internal compare registers with values stored in the
PWMxCOMx and PWMxLEN registers
Direction control when PWM is in H-bridge mode.
0: PWM2 and PWM3 act as output signals while PWM0 and PWM1 are held low
1: PWM0 and PWM1 act as output signals while PWM2 and PWM3 are held low
Set to enable H-bridge mode.
Master enable for PWM.
0: disable all PWM outputs
1: enable all PWM outputs
Description
Reserved. Return 0 on reads.
Set to enable PWM trip functionality.
Reserved.
Description
Reserved. Return 0 on reads.
Write a 1 to clear latched IRQPWMTrip interrupt. Returns 0 on reads.
Write a 1 to clear latched IRQPWM3 interrupt. Returns 0 on reads.
Write a 1 to clear latched IRQPWM2 interrupt. Returns 0 on reads.
Write a 1 to clear latched IRQPWM1 interrupt. Returns 0 on reads.
Write a 1 to clear latched IRQPWM0 interrupt. Returns 0 on reads.
Description
Compare Register 0 data.
Description
Compare Register 1 data.
Rev. C | Page 181 of 196
UG-498
Reset Access
0x0 RW
0x0 RW
0x1 RW
0x0 RW
Reset Access
0x00 Reserved
0x0 RW
0x0 Reserved
Reset Access
0x000 Reserved
0x0 RW1C
0x0 RW1C
0x0 RW1C
0x0 RW1C
0x0 RW1C
Reset Access
0x0 RW
Reset Access
0x0 RW