Analog Devices ADuCM320 Hardware Reference Manual page 117

ADuCM320 Hardware Reference Manual
Master Current Receive Data Count Register
Address: 0x40003414, Reset: 0x0000, Name: I2C1MCRXCNT
Table 162. Bit Descriptions for I2C1MCRXCNT
Bits Bit Name
[15:8] RESERVED
[7:0] COUNT
First Master Address Byte Register
Address: 0x40003418, Reset: 0x0000, Name: I2C1ADR0
Table 163. Bit Descriptions for I2C1ADR0
Bits Bit Name
[15:8] RESERVED
[7:0] ADR0
Second Master Address Byte Register
Address: 0x4000341C, Reset: 0x0000, Name: I2C1ADR1
Table 164. Bit Descriptions for I2C1ADR1
Bits Bit Name
[15:8] RESERVED
[7:0] ADR1
Serial Clock Period Divisor Register
Address: 0x40003424, Reset: 0x1F1F, Name: I2C1DIV
Table 165. Bit Descriptions for I2C1DIV
Bits Bit Name
[15:8] HIGH
[7:0] LOW
Description
Reserved.
Current receive count. This register gives the total number of bytes
received so far. If 256 bytes are requested, this register reads 0 when the
transaction has completed.
Description
Reserved.
Address byte 0. If a 7-bit address is required, Bit 7 to Bit 1 of ADR0 are
programmed with the address and Bit 0 of ADR0 is programmed with the
direction (0 = write, 1 = read). If a 10-bit address is required, Bit 7 to Bit 3 of
ADR0 are programmed with 11110, Bit 2 to Bit 1 of ADR0 are programmed
with the 2 MSBs of the address, and Bit 0 of ADR0 is programmed to 0.
Description
Reserved.
Address byte 1. This register is only required when addressing a slave with
a 10-bit address. Bit 7 to Bit 0 of ADR1 are programmed with the lower 8 bits
of the address.
Description
Serial clock high time. This register controls the clock high time. The timer
is driven by the core clock (PCLK). Use the following equation to derive the
required high time.
HIGH = (REQD_HIGH_TIME/PCLK_PERIOD) – 2.
For example, to generate a 400 kHz SCL with a low time of 1300 ns and a
high time of 1200 ns, with a core clock frequency of 50 MHz:
LOWTIME = 1300 ns/20 ns − 1 = 0x40 (64 decimal).
HIGH = 1200 ns/20 ns − 2 = 0x3A (58 decimal).
This register is reset to 0x1F, which gives an SCL high time of 33 PCLK ticks.
t is also determined by the HIGH.
HD:STA
t = (HIGH − 1) × PCLK_PERIOD.
HD:STA
As t must be 600 ns, with PCLK = 50 MHz, the minimum value for HIGH
HD:STA
is 31. This gives an SCL high time of 660 ns.
Serial clock low time. This register controls the clock low time. The timer is
driven by the core clock (PCLK). Use the following equation to derive the
required low time.
LOW = (REQD_LOW_TIME/PCLK_PERIOD) − 1
This register is reset to 0x1F, which gives an SCL low time of 32 PCLK ticks.
Rev. C | Page 117 of 196
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Reset Access
0x0 R
0x0 R
Reset Access
0x0 R
0x0 RW
Reset Access
0x0 R
0x0 RW
Reset Access
0x1F RW
0x1F RW