Pla; Pla Features; Pla Overview - Analog Devices ADuCM320 Hardware Reference Manual

UG-498

PLA

PLA FEATURES

The ADuCM320 integrates a fully programmable logic array (PLA) that consists of four independent but interconnected PLA blocks.
Each block consists of eight PLA elements: Block X Element 0 to Block X Element 7, where X is the block number. Each
four blocks, resulting in a total of 32 PLA elements: Element 0 to Element 31.

PLA OVERVIEW

Each PLA element contains a two-input lookup table that can be configured to generate any logic output function based on two inputs
and a flip-flop.
BLOCK X ELEMENT 0
BLOCK X ELEMENT 2
BLOCK X ELEMENT 4
BLOCK X ELEMENT 6
BLOCK X ELEMENT 1
BLOCK X ELEMENT 3
BLOCK X ELEMENT 5
BLOCK X ELEMENT 7
WHERE:
BLOCK X IS BLOCK 0 OR BLOCK 1.
PLA_ELEMn IS THE MMR CONTROLING ELEMENT n, n = 0 TO 15.
NC = NO CONNECTION.
1 THE FIRST SELECTION OF MUX0 IS THE FEEDBACK FROM BLOCK X ELEMENT 0, WHERE X IS THE NUMBER OF THE CURRENT BLOCK.
IF THE FIRST ELEMENT IN THE BLOCK IS BEING CONFIGURED, THEN THE FEEDBACK COMES FROM ANOTHER BLOCK.
SEE THE INTERBLOCK CONNECTION DIAGRAM FOR MORE DETAILS.
2
BLOCK 0 AND BLOCK 1 ARE SET IN THE CORRESPONDING BIT IN THE PLA_DIN0 MMR.
BLOCK X ELEMENT 0
BLOCK X ELEMENT 2
BLOCK X ELEMENT 4
BLOCK X ELEMENT 6
BLOCK X ELEMENT 1
BLOCK X ELEMENT 3
BLOCK X ELEMENT 5
BLOCK X ELEMENT 7
WHERE:
BLOCK X IS BLOCK 2 OR BLOCK 3.
PLA_ELEMn IS THE MMR CONTROLING ELEMENT n, n = 16 TO 31.
NC = NO CONNECTION.
1 THE FIRST SELECTION OF MUX0 IS THE FEEDBACK FROM BLOCK X ELEMENT 0, WHERE X IS THE NUMBER OF THE CURRENT BLOCK.
IF THE FIRST ELEMENT IN THE BLOCK IS BEING CONFIGURED, THEN THE FEEDBACK COMES FROM ANOTHER BLOCK.
SEE THE INTERBLOCK CONNECTION DIAGRAM.
2
FOR BLOCK 2 AND BLOCK 3 THE INPUT COMES FROM THE OUTPUT OF ELEMENT(n – 16),
WHERE n IS THE NUMBER OF THE ELEMENT BEING CONFIGURED.
FOR EXAMPLE, FOR ELEMENT 25 THE INPUT TO MUX 2 COMES FROM ELEMENT 9.
THIS ALLOWS GPIO INPUTS TO BE INDIRECTLY CONNECTED TO ELEMENTS IN BLOCK 2 AND BLOCK 3.
In total, 28 GPIO pins are available on each
configured in the GPxCON register as PLA pins before using the PLA.
2
PLA_DIN0[n]
1
0
PLA_ELEMn[10:9]
PLA_ELEMn[6]
1
GPIO INPUT
PLA_ELEMn[8:7]
PLA_ELEMn[5]
Figure 25. PLA Element: Block 0 and Block 1
2
OUTPUT ELEMENT (n – 16)
1
0
PLA_ELEMn[10:9] PLA_ELEMn[6]
1
NC
PLA_ELEMn[8:7]
PLA_ELEMn[5]
Figure 26. PLA Element: Block 2 and Block 3
ADuCM320
ADuCM320 Hardware Reference Manual
PLA_CLK
2
A
LOOKUP
TABLE
B
PLA_ELEMn[4:1]
3
PLA_CLK
2
A
LOOKUP
TABLE
B
PLA_ELEMn[4:1]
3
for the PLA. These include 14 input pins and 14 output pins, which must be
Rev. C | Page 146 of 196
OUTPUT ELEMENT n
4
PLA_ELEMn[0]
OUTPUT ELEMENT n
4
PLA_ELEMn[0]
ADuCM320 has