Register Summary: Analog Comparator; Register Details: Analog Comparator; Changes To Table 25 - Analog Devices ADuCM320 Hardware Reference Manual

UG-498

REGISTER SUMMARY: ANALOG COMPARATOR

The CPU accesses the ADC circuit over a die to die interface (D2D) which increases the execution times of ldr and str instructions.
Accessing AFECOMP takes 8 CPU cycles at 80 MHz to execute.
Table 24. Analog Comparator Register Summary
Address Name
0x40087838 AFECOMP

REGISTER DETAILS: ANALOG COMPARATOR

Analog Comparator Configuration Register
Address: 0x40087838, Reset: 0x0000, Name: AFECOMP
Table 25. Bit Descriptions for AFECOMP
Bits Bit Name
[15:9] RESERVED
8 EN
[7:6] INNEG
[5:4] OUT
3 INV
[2:1] SPEED
0 HYS
Description
Analog comparator configuration register
Description
Reserved.
Powers up and enables comparator.
0: power down and disable comparator
1: power up and enable comparator
Selects comparator negative input signal.
00: AVDD/2
01: AIN5
10: DAC7
11: unused
Connects comparator output to interrupt logic.
0: do not connect output
1: connect output to interrupt logic
Selects output logic state.
0: output is high if +ve input is above −ve input.
1: output is high if +ve input is below −ve input.
Selects comparator speed to falling output.
00: 6 µs
01: 4 µs
10: 4 µs
11: 3 µs
Response time to rising output is 6 µs typical.
Enables comparator hysteresis.
0: disable hysteresis
1: enable hysteresis
Rev. C | Page 36 of 196
ADuCM320 Hardware Reference Manual
Reset RW
0x0000 RW
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW