Analog Devices ADuCM320 Hardware Reference Manual page 175

ADuCM320 Hardware Reference Manual
Bits Bit Name
6 IRQCRY
5 RESERVED
4 ROLL
3 WUFD
2 WUFC
1 WUFB
0 WUFA
Clear Interrupt Register
Address: 0x40002530, Reset: 0x0000, Name: T4CLRI
Table 261. Bit Descriptions for T4CLRI
Bits Bit Name
[15:5] RESERVED
4 ROLL
3 WUFD
2 WUFC
1 WUFB
0 WUFA
Wake-Up Field A—Least Significant 16 Bits Register
Address: 0x4000253C, Reset: 0x1900, Name: T4WUFA0
Table 262. Bit Descriptions for T4WUFA0
Bits Bit Name
[15:0] T4WUFAL
Wake-Up Field A—Most Significant 16 Bits Register
Address: 0x40002540, Reset: 0x0000, Name: T4WUFA1
Table 263. Bit Descriptions for T4WUFA1
Bits Bit Name
[15:0] T4WUFAH
Description
Wake-up status to power-down. Set automatically when any of the
interrupts are still set in the external crystal clock domain. Cleared
automatically when the interrupts are cleared, allowing power down
mode. User code should wait for this bit to be cleared before entering
power-down mode.
Reserved.
Rollover interrupt flag. Used only in free running mode. Set automatically
to indicate a roll over interrupt has occurred. Cleared automatically after a
write to T4CLRI.
T4WUFD interrupt flag. Set automatically to indicate a comparator
interrupt has occurred. Cleared automatically after a write to the
corresponding bit in T4CLRI.
T4WUFC interrupt flag. Set automatically to indicate a comparator
interrupt has occurred. Cleared automatically after a write to the
corresponding bit in T4CLRI.
T4WUFB interrupt flag. Set automatically to indicate a comparator
interrupt has occurred. Cleared automatically after a write to the
corresponding bit in T4CLRI.
T4WUFA interrupt flag. Set automatically to indicate a comparator
interrupt has occurred. Cleared automatically after a write to the
corresponding bit in T4CLRI.
Description
Reserved.
Rollover interrupt clear. Used only in free running mode. Set by user code
to clear a roll over interrupt flag. Cleared automatically after synchronization.
T4WUFD interrupt clear.
T4WUFC interrupt clear. Set by user code to clear a T4WUFC interrupt flag.
Cleared automatically after synchronization.
T4WUFB interrupt clear. Set by user code to clear a T4WUFB interrupt flag.
Cleared automatically after synchronization.
T4WUFA interrupt clear. Set by user code to clear a T4WUFA interrupt flag.
Cleared automatically after synchronization.
Description
Wake-Up Field A low. Least significant 16 bits of Wake-Up Field A.
Description
Wake-Up Field A high. Most significant 16 bits of Wake-Up Field A.
Rev. C | Page 175 of 196
UG-498
Reset Access
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x1900 RW
Reset Access
0x0 RW