Analog Devices ADRV9005 Manuals

Analog Devices ADRV9005 Manuals

Manuals and User Guides for Analog Devices ADRV9005. We have 1 Analog Devices ADRV9005 manual available for free PDF download: Reference Manual

Analog Devices ADRV9005 Reference Manual

Analog Devices ADRV9005 Reference Manual (377 pages)

Brand: Analog Devices | Category: Motherboard | Size: 30 MB

Table of Contents

ADRV9001 System Development User Guide Overview
1
Changes to ADRV9001 System Development User Guide Overview Section
1
Table of Contents
2
How to Use this Document
7
Block Diagram
8
Product Highlights
9
- Adrv9002
  9
- Adrv9003
  11
- Adrv9004
  11
- Adrv9005
  11
- Adrv9006
  11
Added ADRV9005 Section
11
Added ADRV9006 Section
11
- ADRV9001 Product Family Comparison
  12
- Added ADRV9001 Product Family Comparison Section and Table 1; Renumbered Sequentially
  12
ADRV9001 Example Use Cases
13
Software System Architecture Description
33
Software Integration
38
- Hardware Abstraction Layer
  38
- Developing the Application
  43
System Initialization and Shutdown
45
- TES Configuration and Initialization
  45
- API Initialization Sequence
  46
Changes to API Initialization Sequence Section
46
- State Change Timing
  48
- Shutdown Sequence
  48
- System Debugging
  48
- Warm Boot
  50
- Changes to Warm Boot Section and Table 15
  50
- Boot-Up Timing
  52
Added Operating Temperature Considerations Section
52
Changes to Table 16
54
Changes to Warm Boot Boot-Up Section
55
Added Table 17
55
Serial-Peripheral Interface (SPI)
56
- SPI Configuration
  56
- SPI Bus Signals
  56
- SPI Broadcast Mode
  57
- Added SPI Broadcast Mode Section and Figure 27; Renumbered Sequentially
  57
- SPI Data Transfer Protocol
  58
- Added Table 19
  58
- Timing Diagrams
  60
Changes to Timing Diagrams Section
60
- SPI Test
  61
- SPI Main
  61
Data Interface
64
Changes to Enhanced Rx SSI Mode Section
76
- Power Saving for LSSI
  77
- SSI Timing Parameters
  77
- Added Figure 58
  77
- API Programming
  78
- CSSI/LSSI Testability and Debug
  80
Microprocessor and System Control
83
- System Control
  84
- Timing Parameters Control
  84
- API Execution Timing
  98
Clock Generation
99
- Low Power Clock Phase-Lock Loop (LP CLKPLL)
  99
- Arbitrary Sample Rate
  100
Multichip Synchronization
102
- Introduction
  102
- Theory of Operation
  102
- MCS Substates (Internal MCS State Transition)
  105
- MCS Procedure and Status Check
  105
Changes to MCS Procedure and Status Check Section
105
- Sample Delay and Read Delay
  106
- Phase Synchronization
  108
Changes to RF Synthesizer Section
110
Synthesizer Configuration and lo Operation
110
- Clock Synthesizer
  110
- RF Synthesizer
  110
Added RF Synthesizer Frequency Accuracy Section
111
Added Example Frequency Accuracy Calculation Section
111
- Auxiliary Synthesizer
  112
- External lo
  112
- RF PLL Loop Filter Recommendations
  112
- PLL Phase Noise
  112
- API Operation
  114
Changes to Local Oscillator (LO) Change Procedure Section
114
Frequency Hopping
116
- Key Signals
  116
- Modes of Operation
  117
- Changes to Modes of Operation Section and Table 48
  117
- Frequency Hopping Table
  119
Changes to Example 1: Load New Frequencies with Automatic Ping Pong Section
122
Changes to Example 2: Loading a Larger Set of Frequencies with Manual Table Switch Section
123
- Selecting the Channel and Profile
  124
- Frequency Hopping Operation Ranges
  124
- Frequency Hopping Calibrations
  124
- Frequency Hopping Timing
  125
- Additional Frequency Hopping Operations
  132
- Diversity Mode
  136
- Frequency Hopping with Rx/Orx Gain Control
  137
- Special Frequency Hopping Operations
  137
- Integration with Other Advanced Features
  140
- Frequency Hopping API Programming
  141
Transmitter Signal Chain
142
- Data Interface
  142
- Datapath
  142
- Digital Front End (DFE)
  143
- Analog Front End (AFE)
  148
- Transmit Data Chain API Programming
  149
Receiver/Observation Receiver Signal Chain
150
- Receive Data Chain
  152
- Analog Front-End Components
  153
- Digital Front End Components
  155
- Receive Data Chain API Programming
  159
Transmitter/Receiver/Observation Receiver Signal Chain Calibrations
161
- Initial Calibrations
  161
- Tracking Calibrations
  172
Receiver Gain Control
177
- Receiver Datapath
  178
- Gain Control Modes
  183
- Gain Control Detectors
  190
- AGC Clock and Gain Block Timing
  194
- Analog Gain Control API Programming
  195
- Digital Gain Control and Interface Gain (Slicer)
  202
- Digital Gain Control and Interface Gain API Programming
  205
- Usage Recommendations
  206
- TES Configuration and Debug Information
  206
Receiver Demodulator
211
Power Saving and Monitor Mode
218
- Power-Down Modes
  218
- Power-Down/Up Channel in Calibrated State
  219
- Dynamic Interframe Power Saving
  219
- Monitor Mode
  222
Digital Predistortion (DPD)
230
- Background
  230
- ADRV9001 DPD Function
  230
- ADRV9001 DPD Supported Waveforms
  231
- DPD with Frequency Hopping (FH)
  232
- ADRV9001 DPD Performance
  232
- Closed Loop Gain Control (CLGC)
  233
- DPD/CLGC Configuration
  234
- Board Configuration
  244
- Save and Load DPD Coefficients from Last Transmission
  245
- Define the Frequency Region When Performing DPD with FH
  245
- DPD/CLGC API Programming
  246
- DPD Tuning and Testing
  246
- Measuring the CLGC Target Gain
  249
Dynamic Profile Switching (DPS)
251
- Overview
  251
- Initial Calibration with DPS
  251
- Performing DPS on the Fly
  252
- DPS API Programming
  253
- Summary of DPS Limitations
  253
- DPS Operations in TES
  254
Power Amplifier Ramp Control
256
- Power Amplifier Open-Loop Ramp Control
  256
- Power Amplifier Close Loop Ramp Control
  257
General-Purpose Input/Output (GPIO) and Interrupt Configuration
258
- GPIO Operation
  259
- Analog GPIO Operation
  262
- Interrupt
  263
Auxiliary Converters and Temperature Sensor
264
RF Port Interface Information
267
- Transmit Ports: TX1± and TX2
  267
- Receive Ports: RX1A±, RX1B±, RX2A±, and RX2B
  267
- External Local Oscillator Ports: LO1± and LO2
  267
- Device Clock Port: DEV_CLK1
  267
- RF Receiver/Transmitter Ports Impedance Data
  267
- General Receiver Port Interface
  270
- General Transmitter Bias and Port Interface
  273
- Impedance Matching Network Examples
  275
- Receiver RF Port Impedance Matching Network
  276
  - Measurement Data
    279
  - Network
    280
  - Measurement Data
    282
  - Network
    283
  - Measurement Data
    286
  - (Dev_Clk_In)
    286
- DEV_CLK_IN Phase Noise Requirements
  288
  - (MCS) Input
    289
- Recommendations
  290
- Selecting the PCB Material and Stackup
  290
- Fanout and Trace Space Guidelines
  291
- Component Placement and Routing Priorities
  292
- Isolation Techniques Used on the
  305
- Transmitter RF Port Impedance Matching ADRV9001 Evaluation Card
  305
Power-Supply Recommendations
308
ADRV9001 Evaluation System
329
Printed Circuit Board Layout Additional Resources
375
- Q Formatting Standard Description
  375
- Frequently Asked Questions
  376

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