Analog Devices ADuCM320 Hardware Reference Manual page 111

ADuCM320 Hardware Reference Manual
Bits Bit Name
2 STXREQ
1 STXUR
0 STXFSEREQ
Slave Receive Register
Address: 0x40003030, Reset: 0x0000, Name: I2C0SRX
Table 147. Bit Descriptions for I2C0SRX
Bits Bit Name
[15:8] RESERVED
[7:0] I2C0SRX
Slave Transmit Register
Address: 0x40003034, Reset: 0x0000, Name: I2C0STX
Table 148. Bit Descriptions for I2C0STX
Bits Bit Name
[15:8] RESERVED
[7:0] I2C0STX
Hardware General Call ID Register
Address: 0x40003038, Reset: 0x0000, Name: I2C0ALT
Table 149. Bit Descriptions for I2C0ALT
Bits Bit Name
[15:8] RESERVED
[7:0] ALT
Description
Slave transmit request. If EARLYTXR = 0, STXREQ is set when the direction
bit for a transfer is received high. Thereafter, as long as the transmit FIFO is
not full, this bit remains asserted. Initially, it is asserted on the negative
edge of the SCL pulse that clocks in the direction bit (if the device address
matched also).
If EARLYTXR = 1, STXREQ is set when the direction bit for a transfer is
received high. Thereafter, as long as the transmit FIFO is not full this bit
remains asserted. Initially, it is asserted after the positive edge of the SCL
pulse that clocks in the direction bit (if the device address matched also).
This bit is cleared on a read of the I2C0SSTA register.
Slave transmit FIFO underflow. Is set if a master requests data from the
device, and the Tx FIFO is empty for the rising edge of SCL.
Slave Tx FIFO status or early request. If EARLYTXR = 0, this bit is asserted
whenever the slave Tx FIFO is empty.
If EARLYTXR = 1, TXFSEREQ is set when the direction bit for a transfer is
received high. It asserts on the positive edge of the SCL clock pulse that
clocks in the direction bit (if the device address matched also). It only
asserts once for a transfer. It is cleared when read if EARLYTXR is asserted.
Description
Reserved
Slave receive register
Description
Reserved
Slave transmit register
Description
Reserved.
Slave Alt. This register is used in conjunction with I2C0SCON[3] to match a
master generating a hardware general call. It is used in the case where a
master device cannot be programmed with a slave's address and instead
the slave must recognize the master's address.
Rev. C | Page 111 of 196
UG-498
Reset Access
0x0 RC
0x0 RC
0x1 RW
Reset Access
0x0 R
0x0 R
Reset Access
0x0 R
0x0 RW
Reset Access
0x0 R
0x0 RW