Analog Devices ADuCM320 Hardware Reference Manual
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Analog Devices ADuCM320 Hardware Reference Manual

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SCOPE

This reference manual provides a detailed description of the

DISCLAIMER

Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective owners.
AIN0
AIN5
AIN6
AIN15
VDAC0
VDAC7
IDAC0
IDAC3
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
ADuCM320 Hardware Reference Manual
How to Set Up and Use the
ADuCM320

FUNCTIONAL BLOCK DIAGRAM

BUF_VREF2V5
2.5V BAND GAP
14-BIT
MUX
SAR ADC
INTERNAL
CHANNELS:
TEMPERATURE,
AV
, IOV
DD
DD
COMPARATOR
VDAC
VDAC
IDAC
ADuCM320
IDAC
PVDDx
PGND
Figure 1.
Rev. C | Page 1 of 196
ADuCM320
functionality and features.
XTALO XTALI ECLKIN
1.8 V LDO
CLOCK SYSTEM
32.768kHz
16MHz OSC
80MHz PLL
ARM
CORTEX-M3
GPIO PORTS
PROCESSOR
UART
2 × SPI
2
2 × I
C
EXT IRQs
MEMORY
MDIO
2 × 128kB FLASH
PLA
32kB SRAM
DMA
3 × GENERAL
NVIC
PURPOSE TIMER
WATCHDOG TIMER
WAKE-UP TIMER
PWM
RESET SYSTEM
SERIAL WIRE
RESET
UG-498
DGNDx
AVDDx
AGNDx
IOVDDx
IOGNDx
GENERAL
PURPOSE
I/O PORTS
PWM0 TO
PWM6
SWDIO
SWCLK

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Summary of Contents for Analog Devices ADuCM320

  • Page 1: Scope

    Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

  • Page 2: Table Of Contents

    Register Summary: Additional Registers ........ 33     Revision History ................4 Register Details: Additional Registers ........33     Using the ADuCM320 Hardware Reference Manual ....6 Analog Comparator ............... 35     Number Notations ................ 6 Analog Comparator Features ............ 35  ...
  • Page 3 ADuCM320 Hardware Reference Manual UG-498     DMA Interrupts ................61 SPI Operation ................123     DMA Priority ................62 SPI Transfer Initiation .............. 124     Channel Control Data Structure ..........62 SPI Interrupts ................126    ...

  • Page 4: Revision History

    Changes to Register Access Conventions Section ......6 Changes to Digital I/Os Features Section and Digital I/Os Overview Section................86 Changes to Introduction to the ADuCM320 Section ....7 Moved Register Summary: Clock Architecture Section .... 12 Added Inaccessible Bits Section ........... 86 Changes to I/O Pull-Up Enable (GPxPUL) Section ....
  • Page 5 ADuCM320 Hardware Reference Manual UG-498 Changes to Table 119 ..............91 GPIO Port 5 Open Drain Enable Register Section, and Table Changes to Register Details: Digital I/O Section, GPIO Port 141 to Table 145 ................97 Configuration Registers Section, GPIO Port Output Enable Changes to GPIO Port Data Output Registers Section, GPIO Registers Section, Table 120, and Table 121.........

  • Page 6: Using The Aducm320 Hardware Reference Manual

    UG-498 ADuCM320 Hardware Reference Manual USING THE ADuCM320 HARDWARE REFERENCE MANUAL NUMBER NOTATIONS Table 1. Number Notations Notation Description Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0.

  • Page 7: Introduction To The Aducm320

    Up to eight voltage DACs are provided with output ranges programmable to one of two voltage ranges. The DAC outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. On the ADuCM320, four current output DAC sources are provided.

  • Page 8: Memory Organization

    UG-498 ADuCM320 Hardware Reference Manual Communication • UART Industry standard, 16450 UART peripheral Support for DMA • Two I 2-byte transmit and receive FIFOs for the master and slave Support for DMA • Two SPIs Master or slave mode with separate 4-byte Rx and Tx FIFOs Rx and Tx DMA channels •...
  • Page 9 ADuCM320 Hardware Reference Manual UG-498 0xFFFF FFFF VENDOR SPECIFIC 0xE010 0000 0xE00F FFFF PRIVATE PERIPHERAL BUS—EXTERNAL 0xE004 0000 0xE003 FFFF PRIVATE 0xE000 EF00 PERIPHERAL BUS—INTERNAL ADuCM320 MMRs 0xE000 0000 0xE000 E000 0xDFFF FFFF EXTERNAL DEVICE (NOT AVAILABLE IN ADuCM320) 0xA000 0000...

  • Page 10: Clocking Architecture

    UG-498 ADuCM320 Hardware Reference Manual CLOCKING ARCHITECTURE CLOCKING ARCHITECTURE FEATURES ADuCM320 integrates two on-chip oscillators and circuitry for an external crystal and external clock source: • LFOSC is a 32 kHz low power internal oscillator that is used in low power modes.

  • Page 11: Clocking Architecture Block Diagram

    ADuCM320 Hardware Reference Manual UG-498 CLOCKING ARCHITECTURE BLOCK DIAGRAM ACLK (TO LV DIE, ADC) HFXTAL 16MHz OSC 80MHZ SPLL CLKCON0[11] CLKCON5[3] I2C0 CLKCON5[4] CDPCLK PCLK I2C1 (CLKCON1[10:8]) CLKCON5[5] UART PCLK UCLK CLKCON5[6] HFOSC CDD2DCLK (CLKCON1[11]) 16MHz OSC CLKCON5[0] ECLKIN SPI0 P1.0...

  • Page 12: Clocking Architecture Overview

    UG-498 ADuCM320 Hardware Reference Manual CLOCKING ARCHITECTURE OVERVIEW The system clock, UCLK, can be selected from a 16 MHz oscillator or from an 80 MHz PLL output (default). An external clock on P1.0 can also be used for test purposes.

  • Page 13: Register Details: Clock Architecture

    ADuCM320 Hardware Reference Manual UG-498 REGISTER DETAILS: CLOCK ARCHITECTURE Misc Clock Settings Register Address: 0x40028000, Reset: 0x0041, Name: CLKCON0 Table 5. Bit Descriptions for CLKCON0 Bits Bit Name Description Reset Access HFXTALIE High frequency crystal interrupt enable. 0: an interrupt to the core is not generated on a HFXTAL ok or HFXTAL nok...

  • Page 14: 2/2016-Rev. A To Rev. B Changes To Table 7

    UG-498 ADuCM320 Hardware Reference Manual Clock Dividers Register Address: 0x40028004, Reset: 0x0200, Name: CLKCON1 Table 6. Bit Descriptions for CLKCON1 Bits Bit Name Description Reset Access [15:12] RESERVED Reserved. CDD2DCLK D2DCLK divide bits. 0: D2D_CLK frequency = HCLK frequency. 1: D2D_CLK frequency = half of HCLK frequency.

  • Page 15: Added Clocking Status Register Section And Table 8; Renumbered Sequentially

    ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access UCLKSPI1OFF SPI1 clock user control. This bit disables the UCLK_SPI1 clock. It controls the gate on UCLK_SPI1 in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3 the UCLK_SPI1 is always off and this bit has no effect.

  • Page 16: Power Management Unit

    UG-498 ADuCM320 Hardware Reference Manual POWER MANAGEMENT UNIT POWER MANAGEMENT UNIT FEATURES The power management unit (PMU) controls the different power modes of the ADuCM320. Four power modes are available: • Active • CORE_SLEEP • SYS_SLEEP • Hibernate POWER MANAGEMENT UNIT OVERVIEW The Cortex-M3 sleep modes are linked to the PMU modes and are described in this section.

  • Page 17: Code Examples

    ADuCM320 Hardware Reference Manual UG-498 CODE EXAMPLES Code Example to Enter Power Saving Modes SCB->SCR = 0x04; // sleepdeep mode pADI_PWRCTL->PWRKEY = 0x4859; // key1 pADI_PWRCTL->PWRKEY = 0xF27B; // key2 pADI_PWRCTL->PWRMOD = 0x3; // Hibernate __DSB(); __nop(); __nop(); __nop(); __nop();...

  • Page 18: Register Summary: Power Management Unit

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: POWER MANAGEMENT UNIT Table 9. Power Management Register Summary Address Name Description Reset 0x40002400 PWRMOD Power modes 0x0000 0x40002404 PWRKEY Key protection for PWRMOD 0x0000 REGISTER DETAILS: POWER MANAGEMENT UNIT Power Modes Register Address: 0x40002400, Reset: 0x0000, Name: PWRMOD Table 10.

  • Page 19: Arm Cortex-M3 Processor

    ARM CORTEX-M3 PROCESSOR OPERATION Several ARM Cortex-M3 processor components are flexible in their implementation. This section details the actual implementation of these components in the ADuCM320. Serial Wire Debug (SW/JTAG-DP) ADuCM320 only supports the serial wire interface via the SWCLK and SWDIO pins.

  • Page 20: Arm Cortex-M3 Processor Related Documents

    • Interrupt masking In addition, the NVIC has a nonmaskable interrupt (NMI) input. The NVIC is implemented on the ADuCM320, and more details are available in the System Exceptions and Peripheral Interrupts section. Wake-Up Interrupt Controller (WIC) ADuCM320 has a modified WIC, which provides the lowest possible power-down current. This feature is transparent to the user and more details are available in the Power Management Unit section.

  • Page 21: Adc Circuit

    ADuCM320 Hardware Reference Manual UG-498 ADC CIRCUIT ADC CIRCUIT FEATURES  ADuCM320 incorporates a fast, multichannel, 16-bit ADC. The ADC is specified to be 14-bit accurate.  Flexible input multiplexer supporting 16 external inputs and 11 internal channels. The internal channels include the following: Temperature sensor channel.

  • Page 22: Adc Circuit Overview

    UG-498 ADuCM320 Hardware Reference Manual ADC CIRCUIT OVERVIEW ADuCM320 incorporates a fast, multichannel, 16-bit ADC. The ADC is specified to be 14-bit accurate. It can operate from a 2.9 V to 3.6 V supply and is capable of providing a throughput of up to 1 MSPS. This ADC block provides the user with a multichannel multiplexer, input buffer for high impedance input channels, on-chip reference, and successive approximation register (SAR) ADC.

  • Page 23: Adc Transfer Function

    ADuCM320 Hardware Reference Manual UG-498 ADC TRANSFER FUNCTION Single-Ended Mode In single-ended mode, the input range is 0 to V . The output coding is straight binary with 1 LSB = FS/65,536; or, /65,536 = 2.51 V/65,536 = 38.30 μV The data values in ADCDATx are aligned such that the MSB is in ADCDATx[27] and, therefore, the LSB is in ADCDATx[12].

  • Page 24: Adc Typical Setup Sequence

    1 before starting another sequence and reconfiguring the ADC back to continuous conversion mode. This ensures that the sequencer restarts with the first selected channel in ADCSEQ. ADC INPUT BUFFER An optional input buffer can be enabled for any ADC input channel on the ADuCM320. The control register IBUFCON controls the input buffer switches as follows: •...

  • Page 25: Adc Support Circuits

    ADuCM320 Hardware Reference Manual UG-498 To calculate the die temperature, use the following formula: T − T = (V − V ) × K TREF where: T is the temperature result. is 25°C. is the average ADC result from two consecutive conversions.

  • Page 26: Changes To Adc Voltage Reference Selection Section

    UG-498 ADuCM320 Hardware Reference Manual ADC Channel Sequencer An ADC sequencer is provided to reduce the processor overhead of sampling and reading individual channels. The ADC sequencer allows a user to select the number and order of ADC input channels that the ADC samples and provides a single interrupt source that is asserted when the sequence ends.

  • Page 27: Added Figure 8; Renumbered Sequentially

    ADuCM320 Hardware Reference Manual UG-498 AFEREFC[0] AFEREFC[1] AFEREFC[3] AFEREFC[2] 1.2V 2.5V BUF_VRFF2.5B GAIN STAGE DRIVER BUFFER ADC CAPP 2.5V ADCCON[7] VDAC AVDD DACxCON[1:0] Figure 8. System Reference Voltage Block Diagram Rev. C | Page 27 of 196...

  • Page 28: Register Summary: Adc Circuit

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: ADC CIRCUIT The CPU accesses the ADC circuit over a die to die interface (D2D) which increases the execution times of ldr and str instructions. 32 bit MMRs have addresses 0x40086xxx and take 8 CPU cycles at 80 MHz to execute. 16 bit MMRs have addresses 0x40082xxx and take 6 CPU cycles at 80 MHz to execute.

  • Page 29: Register Details: Adc Circuit

    ADuCM320 Hardware Reference Manual UG-498 REGISTER DETAILS: ADC CIRCUIT ADC Configuration Register Address: 0x40082174, Reset: 0x0280, Name: ADCCON Table 13. Bit Descriptions for ADCCON Bits Bit Name Description Reset Access [15:11] RESERVED Reserved. SOFT_RESET Software reset ADC. ADC power up.

  • Page 30: Change To Table 14

    UG-498 ADuCM320 Hardware Reference Manual ADCx Data and Flags Register Address: 0x40086000 to 0x4008606C (Increments of 0x4), Reset: 0x00000000, Name: ADCDAT0 to ADCDAT27 At the end of each conversion, the ADC writes the data to the appropriate ADCDATx MMR, where x is 0 to 27. This process takes 2 ADC clock cycles, which at 20 MHz means 100 ns.

  • Page 31: Changes To Table 16

    ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access [7:5] RESERVED Reserved [4:0] ADCCP Select ADC channel. 0x1F 0x0: AIN0. 0x1: AIN1. 0x2: AIN2. 0x3: AIN3. 0x4: AIN4. 0x5: AIN5. 0x6: AIN6. 0x7: AIN7. 0x8: AIN8. 0x9: AIN9.

  • Page 32: Changes To Table 17

    UG-498 ADuCM320 Hardware Reference Manual ADC Sequencer Configuration Register Address: 0x4008608C, Reset: 0x0008C631, Name: ADCSEQC Table 17. Bit Descriptions for ADCSEQC Bits Bit Name Description Reset Access [31:28] RESERVED Reserved. [27:20] Define programmable delay of 0 to 254 between sequences. A delay of 255 causes a halt after one sequence.

  • Page 33: Register Summary: Additional Registers

    ADuCM320 Hardware Reference Manual UG-498 REGISTER SUMMARY: ADDITIONAL REGISTERS The CPU accesses these additional registers over a die to die interface (D2D) which increases the execution times of ldr and str instructions. The 32 bit MMRs have addresses of 0x40087xxx and take 8 CPU cycles at 80 MHz to execute. The 8 bit MMRs have addresses of 0x40081xxx and take 5 CPU cycles at 80 MHz to execute.

  • Page 34: Changes To Table 23

    UG-498 ADuCM320 Hardware Reference Manual Reference Configuration Register Address: 0x40087834, Reset: 0x00, Name: AFEREFC Table 23. Bit Descriptions for AFEREFC Bits Bit Name Description Reset Access [7:4] RESERVED Reserved. Bypass the internal reference, and select the external reference. 0: select internal 2.51 V reference 1: select external 2.51 V reference...

  • Page 35: Analog Comparator

    ADuCM320 Hardware Reference Manual UG-498 ANALOG COMPARATOR ANALOG COMPARATOR FEATURES The analog comparator compares two analog signals and gives an output indicating which of the input signals is bigger. This output can generate an interrupt ANALOG COMPARATOR OVERVIEW The positive input of the comparator is shared with AIN6.

  • Page 36: Register Summary: Analog Comparator

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: ANALOG COMPARATOR The CPU accesses the ADC circuit over a die to die interface (D2D) which increases the execution times of ldr and str instructions. Accessing AFECOMP takes 8 CPU cycles at 80 MHz to execute.

  • Page 37: Idacs

    ADuCM320 Hardware Reference Manual UG-498 IDACs IDAC FEATURES ADuCM320 provides four IDACs. These are low noise, low drift current source outputs.  IDAC0, IDAC1, IDAC2 and IDAC3: 0 mA to 150 mA full-scale output, bias current setting for optical laser.

  • Page 38: Changes To Case 2-Turn On Idac2 But To Set The Output To 0 Ma With The Lowest Possible Offset Section

    UG-498 ADuCM320 Hardware Reference Manual IDAC Data Register The IDAC output is controlled by an internal 11-bit and 5-bit DAC. The 11-bit DAC (IDACxDAT[27:17]) controls the most significant bits. The 5-bit DAC (IDACxDAT[16:12]) controls the LSBs. The two MSBs of the 5-bit DAC (IDACxDAT[16:15]) overlap the two LSBs of the 11-bit DAC (IDACxDAT[18:17]) as shown in Figure 10.

  • Page 39: Added Idac Thermal Shutdown Section

    ADuCM320 Hardware Reference Manual UG-498 IDAC Thermal Shutdown ADuCM320 has an internal temperature sensor that monitors the die temperature. This temperature sensor can be monitored as an ADC input channel; the measured voltage is proportional to die temperature. See the Temperature Sensor Settings section for more information.

  • Page 40: Register Summary: Idac

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: IDAC The CPU accesses the IDAC circuit over a die to die interface (D2D) which increases the execution times of ldr and str instructions. The 32-bit MMRs have addresses of 0x40086xxx and take 8 CPU cycles at 80 MHz to execute.
  • Page 41 ADuCM320 Hardware Reference Manual UG-498 IDAC1 Data Register Address: 0x40086808, Reset: 0x00000000, Name: IDAC1DAT Table 30. Bit Descriptions for IDAC1DAT Bits Bit Name Description Reset Access [31:28] RESERVED Reserved. Write 0. [27:17] DATH IDAC1 high data. [16:12] DATL IDAC1 low data.
  • Page 42 UG-498 ADuCM320 Hardware Reference Manual IDAC2 Control Register Address: 0x40086814, Reset: 0x01, Name: IDAC2CON Table 33. Bit Descriptions for IDAC2CON Bits Bit Name Description Reset Access IDAC2 clear bit. 0: clear IDAC2DAT 1: enable write SHT_EN IDAC2 shutdown enable. Enables automatic shutdown in case of overtemperature.

  • Page 43: Vdacs

    ADuCM320 Hardware Reference Manual UG-498 VDACs VDAC FEATURES ADuCM320 has eight VDACs. The specified load resistance is greater than 5 kΩ, and the specified capacitance is less than 100 pF. VDAC BLOCK DIAGRAM STRING DAC DAC_BUF DACOUT Figure 11. Output Mode Capacitor Load ≤ 100 pF...

  • Page 44: Register Summary: Vdac

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: VDAC The CPU accesses the VDAC circuit over a die to die interface (D2D), which increases the execution times of ldr and str instructions. The 32-bit MMRs have addresses of 0x40086xxx and take 8 CPU cycles at 80 MHz to execute. The 16-bit MMRs have addresses of 0x40082xxx and take 6 CPU cycles at 80 MHz to execute.
  • Page 45 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access [7:5] RESERVED Reserved. DAC1 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. [3:2] RESERVED Reserved. [1:0] DAC1 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC.
  • Page 46 UG-498 ADuCM320 Hardware Reference Manual DAC4 Control Register Address: 0x40082410, Reset: 0x0100, Name: DAC4CON Table 41. Bit Descriptions for DAC4CON Bits Bit Name Description Reset Access [15:9] RESERVED Reserved. DAC4 power down. 0: DAC4 is powered up 1: DAC4 is powered down and output is floating...
  • Page 47 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access DAC6 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately 1: DAC enable. [3:2] RESERVED Reserved. [1:0] DAC6 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC.
  • Page 48 UG-498 ADuCM320 Hardware Reference Manual DAC2 Data Register Address: 0x4008640C, Reset: 0x00000000, Name: DAC2DAT Table 47. Bit Descriptions for DAC2DAT Bits Bit Name Description Reset Access [31:28] RESERVED Reserved. Write 0. [27:16] DAC2 data. [15:0] RESERVED Reserved. Write 0. DAC3 Data Register Address: 0x40086410, Reset: 0x00000000, Name: DAC3DAT Table 48.

  • Page 49: System Exceptions And Peripheral Interrupts

    Type Priority Description Reset −3 (highest) Any reset. −2 Nonmaskable interrupt not connected on the ADuCM320. Hard fault −1 All fault conditions if the corresponding fault handler is not enabled. Memory management Programmable Memory management fault; access to invalid locations.
  • Page 50 UG-498 ADuCM320 Hardware Reference Manual Position No. Vector Wake Up Processor from Mode 1 Wake Up Processor from Mode 2 or Mode 3 SPI1 I2C0 slave I2C0 master PLA 0 PLA 1 DMA error DMA Channel 0 (SPI0 Tx) done...
  • Page 51 ADuCM320 Hardware Reference Manual UG-498 To set the priority of a peripheral interrupt, the IPRx bits can be set appropriately or, alternatively, the NVIC_SetPriority() function can be called. For example, NVIC_SetPriority(TIMER0_IRQn, 2) configures the GP Timer 0 interrupt with a priority level of 2.
  • Page 52 UG-498 ADuCM320 Hardware Reference Manual Table 55. NVIC Registers Address Analog Devices Header File Name Description Access 0xE000E004 ICTR Shows the number of interrupt lines that the NVIC supports. 0xE000E010 STCSR SYSTICK control and status register. 0xE000E014 STRVR SYSTICK reload value register.

  • Page 53: External Interrupt Configuration

    ADuCM320 Hardware Reference Manual UG-498 EXTERNAL INTERRUPT CONFIGURATION Seven external interrupts are implemented. These seven external interrupts can be separately configured to detect any combination of the following type of events: • Edge: rising edge, falling edge, or both rising and falling edges. An interrupt signal (pulse) is sent to the NVIC upon detecting a transition from low to high, high to low, or on either high to low or low to high.
  • Page 54 UG-498 ADuCM320 Hardware Reference Manual Bits Bit Name Description Reset Access [6:4] IRQ1MDE External Interrupt 1 mode registers. 000: rising edge 001: falling edge 010: rising or falling edge 011: high level 100: low level 101: falling edge (same as 001)
  • Page 55 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access IRQ4EN External Interrupt 4 enable bit. 0: External Interrupt 4 disabled 1: External Interrupt 4 enabled [2:0] IRQ4MDE External Interrupt 4 mode registers. 000: rising edge 001: falling edge...

  • Page 56: Low Voltage Analog Die Interrupt Configuration

    UG-498 ADuCM320 Hardware Reference Manual LOW VOLTAGE ANALOG DIE INTERRUPT CONFIGURATION Two interrupt lines are available between the low voltage analog die and the interrupt controller on the digital die. These two interrupt lines are the outputs of two multiplexers of multiple interrupt sources from the low voltage analog die.

  • Page 57: Register Summary: Low Voltage Die Interrupts

    ADuCM320 Hardware Reference Manual UG-498 REGISTER SUMMARY: LOW VOLTAGE DIE INTERRUPTS Table 61. Low Voltage Die Interrupts Register Summary Address Name Description Reset 0x40083004 INTCLR Interrupt clear register 0x0000 0x40083008 INTSEL Interrupt mask register 0x0000 0x4008300C INTSTA Interrupt status register...
  • Page 58 UG-498 ADuCM320 Hardware Reference Manual Interrupt Status Register Address: 0x4008300C, Reset: 0x0000, Name: INTSTA Table 64. Bit Descriptions for INTSTA Bits Bit Name Description Reset Access WRECC_ERR Write data ECC error interrupt status. RDECC_ERR Read data ECC error interrupt status.

  • Page 59: Reset

    ADuCM320 Hardware Reference Manual UG-498 RESET RESET FEATURES There are four kinds of resets: • External reset • Power-on reset • Watchdog timeout • Software system reset RESET OPERATION The software system reset is provided as part of the Cortex-M3 processor. To generate a software system reset, the NVIC_SystemReset() function must be called.

  • Page 60: Register Summary: Reset

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: RESET Table 66. Reset Register Summary Address Name Description Reset 0x40002408 RSTCFG Reset configuration 0x0000 0x4000240C RSTKEY Key protection for RSTCFG 0x0000 0x40002440 RSTSTA Reset status 0x0000 0x40082C34 LVRST LV die reset configuration...

  • Page 61: Dma Controller

    ADuCM320 Hardware Reference Manual UG-498 DMA CONTROLLER DMA FEATURES • 14 dedicated and independent DMA channels. • Two programmable priority levels for each DMA channel. Each priority level arbitrates using a fixed priority that is determined by the DMA channel number.

  • Page 62: Dma Priority

    UG-498 ADuCM320 Hardware Reference Manual The DMA controller fetches channel control data structures located in the SRAM memory to perform data transfers. When enabled to use DMA operation, the DMA-capable peripherals request the DMA controller for transfer. At the end of the programmed number of DMA transfers for a channel, the DMA controller generates an interrupt corresponding to that channel.

  • Page 63: Control Data Configuration

    ADuCM320 Hardware Reference Manual UG-498 Example Code: Define DMA Structures To define DMA structures, memset(dmaChanDesc,0x0, sizeof(dmaChanDesc)); // Set up the DMA base address pointer register. uiBasPtr = (unsigned int)&dmaChanDesc; // Set up the DMA base pointer. pADI_DMA->DMACFG = 1; // Enable DMA controller pADI_DMA->DMAPDBPTR = uiBasPtr;...

  • Page 64: Dma Transfer Types (Chnl_Cfg[2:0])

    UG-498 ADuCM320 Hardware Reference Manual Bits Name Description [25:24] SRC_SIZE Size of the source data. 00: byte. 01: half word. 10: word. 11: reserved. [23:18] RESERVED Undefined. Write as 0. [17:14] R_POWER Set these bits to control how many DMA transfers can occur before the controller re-arbitrates. Must be set to 0000 for all DMA transfers involving peripherals.

  • Page 65: Changes To Table 76

    ADuCM320 Hardware Reference Manual UG-498 Autorequest (CHNL_CFG[2:0] = 010) When the controller operates in this mode, it is only necessary for the controller to receive a single request to enable it to complete the entire DMA cycle. This allows a large data transfer to occur without significantly increasing the latency for servicing higher priority requests or requiring multiple requests from the processor or peripheral.

  • Page 66: Address Calculation

    UG-498 ADuCM320 Hardware Reference Manual Peripheral Scatter-Gather (CHNL_CFG[2:0] = 110 or 111) In peripheral scatter-gather mode, the controller must be configured to use both the primary and alternate data structure. The controller uses the primary data structure to program the control structure of the alternate data structure. The alternate data structure is used for actual data transfers, and each transfer takes place using the alternate data structure with a basic DMA transfer.

  • Page 67: Register Summary: Dma

    ADuCM320 Hardware Reference Manual UG-498 REGISTER SUMMARY: DMA Table 77. DMA Register Summary Address Name Description Reset 0x40010000 DMASTA DMA status 0x000F0000 0x40010004 DMACFG DMA configuration 0x00000000 0x40010008 DMAPDBPTR DMA channel primary control data base pointer 0x00000000 0x4001000C DMAADBPTR DMA channel alternate control data base pointer...
  • Page 68 UG-498 ADuCM320 Hardware Reference Manual DMA Configuration Register Address: 0x40010004, Reset: 0x00000000, Name: DMACFG Table 79. Bit Descriptions for DMACFG Bits Bit Name Description Reset Access [31:1] RESERVED Reserved. Undefined. MENABLE Controller enable. 0: disable controller 1: enable controller DMA Channel Primary Control Data Base Pointer Register Address: 0x40010008, Reset: 0x00000000, Name: DMAPDBPTR The DMAPDBPTR register must be programmed to point to the primary channel control base pointer in the system memory.
  • Page 69 ADuCM320 Hardware Reference Manual UG-498 DMA Channel Request Mask Set Register Address: 0x40010020, Reset: 0x00000000, Name: DMARMSKSET Table 83. Bit Descriptions for DMARMSKSET Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. Reserved, reads back 0. [13:0] CHREQMSET Mask requests from DMA channels. This register disables DMA requests from peripherals.
  • Page 70 UG-498 ADuCM320 Hardware Reference Manual DMA Channel Enable Clear Register Address: 0x4001002C, Reset: 0x00000000, Name: DMAENCLR Table 86. Bit Descriptions for DMAENCLR Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. Undefined. [13:0] CHENCLR Disable DMA channels. This register allows for the disabling of DMA channels. Reading the register returns the enable status of the channels.
  • Page 71 ADuCM320 Hardware Reference Manual UG-498 DMA Channel Priority Set Register Address: 0x40010038, Reset: 0x00000000, Name: DMAPRISET Table 89. Bit Descriptions for DMAPRISET Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. Undefined. [13:0] CHPRISET Configure channel for high priority. This register enables the user to you to configure a DMA channel to use the high priority level.

  • Page 72: Changes To Protection, Integrity Section

    UG-498 ADuCM320 Hardware Reference Manual DMA Channel Bytes Swap Enable Set Register Address: 0x40010800, Reset: 0x00000000, Name: DMABSSET Table 92. Bit Descriptions for DMABSSET Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. Undefined. [13:0] CHBSWAPSET Byte swap status. This register is used to configure a DMA channel to use byte. Each bit of the register represents the corresponding channel number in the DMA controller.

  • Page 73: Flash Controller

    Information space of Flash 0 and Flash 1 is located at Address 0x40000 to Address 0x40FFF and is divided up between kernel space, test space, and calibration space. Information space is reserved for use by Analog Devices. Upon a reset, the hardware forces the part to execute from the start of information space to copy calibration and configuration values to appropriate MMRs.

  • Page 74: Flash Memory Operation

    UG-498 ADuCM320 Hardware Reference Manual The kernel code cannot be accessed by the user. A user can read 16 bytes of Flash 0 information space at Address 0x407E8 to Address 0x407F7. These locations contain ManfID0, ManfID1, and the next eight bytes, which are reserved. ManfID0 and ManfID1 contain traceability information to uniquely identify every part sold.

  • Page 75: Changes To Writing To Flash Section

    ADuCM320 Hardware Reference Manual UG-498 SIGNATURE. ADDRESS 0x1FFFC RESERVED. ADDRESS: 0x1FFF8 USER READ PROTECTION KEY 1. ADDRESS: 0x1FFF4 USER WRITE PROTECTION PATTERN 1 [31:0] ADDRESS: 0x1FFF0 RESERVED. ADDRESS: 0x1FFEC USERFAAKEY1 [31:0] ADDRESS: 0x1FFE8 REST OF THE UPPERMOST PAGE IN USER SPACE Figure 15.

  • Page 76: Added Ecc Error Handling Section, Ecc Error During Read Section, And Ecc Error During Execution Of Sign Command Section

    UG-498 ADuCM320 Hardware Reference Manual Signature The signature is used to check the integrity of the flash device. The signature is calculated from the lowest 32-bit word to the second highest 32-bit word in the selected block. The signature is a 24-bit CRC with an initial value of 0xFFFFFF and the following polynomial: + x + 1 The data is pushed into the CRC polynomial until the specified end address is reached.

  • Page 77: Changes To Memory Cache Section

    ADuCM320 Hardware Reference Manual UG-498 The following code illustrates how the CRC is calculated and how to compare it to the result of the SIGN command. int FeeCrc(int iLen,int *aiData) int i1,i2,iCrc; iCrc = 0xffffffff; //Seed value. for(i1=0; i1<iLen; i1++) //Starting at lowest address.

  • Page 78: Flash Protection

    UG-498 ADuCM320 Hardware Reference Manual ECC Error Handling During the signature check, the error checking and correcting (ECC) is checked on each 72-bit flash read (64-bit flash read and 8-bit ECC). If errors are corrected by the ECC, the ERRDETECTED flag in the status register, FEESTA, is set after the signature check is completed.

  • Page 79: Changes To Table 95 And Table 96

    (USERFAAKEY.). The user must set the key as two 32-bit values near the top of each user flash block. Supplying this key to Analog Devices allows access to user code for debug purposes.

  • Page 80: Changes To Table 95 And Table 96

    UG-498 ADuCM320 Hardware Reference Manual Flash DMA Support Flash controller operations can be supported by DMA. This feature is software configurable. The two flash blocks are independent, meaning that the user can continue executing from one block while programming another block. The DMA is very useful for this because the core only needs to initiate the write to flash, and then the DMA finishes executing the code in the background, triggering an interrupt when the operation is complete.
  • Page 81 ADuCM320 Hardware Reference Manual UG-498 Flash Controller Performance and Command Duration All flash functions are slower than the CPU execution speed. The CPU Execution Speed section details the slight penalty of slower flash reads. All other flash operations are significantly slower, as detailed in Table 94.

  • Page 82: Register Summary: Flash Controller

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: FLASH CONTROLLER Table 95. Flash Controller Register Summary Address Name Description Reset 0x40018000 FEESTA Status register 0x00000000 0x40018004 FEECON0 Command control register: interrupt enable register 0x00000000 0x40018008 FEECMD Command register 0x00000000 0x4001800C FEEFLADR...
  • Page 83 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access [19:17] ECCCOUNTFLASH 0 This is a 3-bit counter that reflects the number of 1-bit ECC read errors in Flash 0 after FEESTA[10:9] = 0x2 and before FEESTA is read. This counter does not count on ECC 2 bit errors.

  • Page 84: Changes To Cache Status Register Section

    UG-498 ADuCM320 Hardware Reference Manual Bits Bit Name Description Reset Access WRALMOSTDONE Write almost complete. Keyhole registers open for access. This bit flags the earliest point at which the flash controller data and address may be updated for the next command without affecting an active flash command operation.

  • Page 85: Changes To Cache Setup Register Section And Cache Key Register Section

    ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access 00100: WRITE. Use this command to write to flash locations. This command needs a user key for writing into write protection location and user flash failure analysis key (USERFAAKEY) location. No key is required for other flash locations. This command takes the address and data from the FEEADR and FEEFLDATA keyhole registers.

  • Page 86: Added Ecc Enable/Disable, Error Response Register Section, Flash 0 Ecc Error Address Register Section, Flash 1 Ecc Error Address Register Section, And Table 112 To Table 114; Renumbered Sequentially

    UG-498 ADuCM320 Hardware Reference Manual Upper Page Address Register Address: 0x4001801C, Reset: 0x00000000, Name: FEEADR1 Table 103. Bit Descriptions for FEEADR1 Bits Bit Name Description Reset Access [31:19] RESERVED Return 0 when read. [18:11] PAGEADDR1 Used by SIGN command for specifying the endpage address. See the description of this command in FEECMD.

  • Page 87: Changes To I/O Pull-Up Enable (Gpxpul) Section

    ADuCM320 Hardware Reference Manual UG-498 User Setup Register Address: 0x40018038, Reset: 0x0000001X, Name: FEECON1 This register is key-protected, so the key (0xF123F456) must be entered in FEEKEY. After writing to FEECON1, a value other than 0xF123F456 must be written again to FEEKEY to reassert the key protection.

  • Page 88: Changes To Open-Drain Enable (Gpxode) Section

    UG-498 ADuCM320 Hardware Reference Manual ECC Enable/Disable, Error Response Register Address: 0x40018064, Reset: 0x00000000, Name: FEEECCCONFIG This register is key-protected, so the key (0x5ECCACCE) must be entered in FEEKEY. After writing to FEECCCONFIG the key is cleared. Table 112. Bit Descriptions for FEEECCCONFIG...
  • Page 89 ADuCM320 Hardware Reference Manual UG-498 Cache Status Register Address: 0x400180C0, Reset: 0x00000002, Name: CACHESTAT Table 115. Bit Descriptions for CACHESTAT Bits Bit Name Description Reset Access [31:20] RESERVED Reserved. DLOCK This bit is set when D-Cache is locked and cleared when D-Cache is unlocked.

  • Page 90: Silicon Identification

    UG-498 ADuCM320 Hardware Reference Manual SILICON IDENTIFICATION ADuCM320 has two silicon die, and each die has a register that identifies the silicon. The CHIPID register contains the digital die silicon version in Bits[3:0] and the part identification in Bits[15:4]. The LVID register contains the low voltage die silicon version.

  • Page 91: Digital I/Os

    ADuCM320 Hardware Reference Manual UG-498 DIGITAL I/Os DIGITAL I/Os FEATURES ADuCM320 features multiple general-purpose bidirectional digital input/output (GPIO) pins. Most of the GPIO pins have multiple functions, configurable by user code. At power up, all but one of these pins are configured as GPIOs; one pin reflects the state of the POR.
  • Page 92 UG-498 ADuCM320 Hardware Reference Manual I/O Pull-Up Enable (GPxPUL) In input mode, GPxPUL enables/disables internal pull-ups/pull-downs. All Port 0 to Port 3 pins have internal pull-ups, and the Port 4 and Port 5 pins have pull-downs. The pull-ups/pull-downs are implemented as MOS devices, with typical performance shown in Figure 17 and Figure 18.
  • Page 93 ADuCM320 Hardware Reference Manual UG-498 I/O Data In Enable (GPxIE) GPxIE enables the GPIO pin input levels to be available in GPxIN. Open-Drain Enable (GPxODE) GPxODE configures pins in output mode to open-drain mode. For P0 to P3 in this mode, the outputs can sink current if the corresponding bit in GPxOUT.y is low.

  • Page 94: Digital Port Multiplex

    UG-498 ADuCM320 Hardware Reference Manual DIGITAL PORT MULTIPLEX This block provides control over the GPIO functionality of specified pins because some of the pins offer the choice to work as a GPIO or to have other specific functions. Table 121. GPIO Multiplex Table...
  • Page 95 ADuCM320 Hardware Reference Manual UG-498 Configuration Modes GPIO P2.5 P2.6 GPIO/IRQ7 PLAO[20] (GP2CON[13:12] = 0x0) (GP2CON[13:12] = 0x3) P2.7 GPIO/IRQ8 PLAO[21] (GP2CON[15:14] = 0x0) (GP2CON[15:14] = 0x3) GP3—GP3CON Controls These Bits P3.0 GPIO PRTADDR0 PLAI[12] (GP3CON[1:0] = 0x0) (GP3CON[1:0] = 0x1) (GP3CON[1:0] = 0x3) P3.1...

  • Page 96: Register Summary: Digital I/O

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: DIGITAL I/O Table 122. GPIO Register Summary Address Name Description Reset 0x40020000 GP0CON GPIO Port 0 configuration 0x0000 0x40020004 GP0OE GPIO Port 0 output enable 0x00 0x40020008 GP0PUL GPIO Port 0 pull-up enable...

  • Page 97: Register Details: Digital I/O

    ADuCM320 Hardware Reference Manual UG-498 Address Name Description Reset 0x40020244 GP5OE GPIO Port 5 output enable 0x00 0x40020248 GP5PUL GPIO Port 5 pull-down enable 0x4002024C GP5IE GPIO Port 5 input path enable 0x40020250 GP5IN GPIO Port 5 registered data input...
  • Page 98 UG-498 ADuCM320 Hardware Reference Manual GPIO Port Pull-Up Enable Registers Address: 0x40020008, Reset: 0x00, Name: GP0PUL Address: 0x40020048, Reset: 0x00, Name: GP1PUL Address: 0x40020088, Reset: 0x08, Name: GP2PUL Address: 0x400200C8, Reset: 0x00, Name: GP3PUL Table 125. Bit Descriptions for GP0PUL, GP1PUL, GP2PUL, GP3PUL...
  • Page 99 ADuCM320 Hardware Reference Manual UG-498 GPIO Port Data Output Registers Address: 0x40020014, Reset: 0x0000, Name: GP0OUT Address: 0x40020054, Reset: 0x0000, Name: GP1OUT Address: 0x40020094, Reset: 0x0000, Name: GP2OUT Address: 0x400200D4, Reset: 0x0000, Name: GP3OUT Address: 0x40020114, Reset: 0x0000, Name: GP4OUT Address: 0x40020254, Reset: 0x0000, Name: GP5OUT Table 129.
  • Page 100 UG-498 ADuCM320 Hardware Reference Manual GPIO Port Pin Toggle Registers Address: 0x40020020, Reset: 0x00, Name: GP0TGL Address: 0x40020060, Reset: 0x00, Name: GP1TGL Address: 0x400200A0, Reset: 0x00, Name: GP2TGL Address: 0x400200E0, Reset: 0x00, Name: GP3TGL Address: 0x40020120, Reset: 0x00, Name: GP4TGL Address: 0x40020260, Reset: 0x00, Name: GP5TGL Table 132.

  • Page 101: I 2 C Serial Interface

    Four 7-bit device addresses or one 10-bit address and two 7-bit addresses in the slave Repeated starts in master and slave modes Clock stretching can be enabled by other devices on the bus without causing any issues with the ADuCM320; however, the ADuCM320...
  • Page 102 UG-498 ADuCM320 Hardware Reference Manual Addressing Modes 7-Bit Addressing The I2CxID0, I2CxID1, I2CxID2, and I2CxID3 registers contain the slave device IDs. The device compares the four I2CxIDx registers to the address byte. To be correctly addressed, the seven MSBs of either ID register must be identical to that of the seven MSBs of the first received address byte.

  • Page 103: I 2 C Operating Modes

    ADuCM320 Hardware Reference Manual UG-498 The bit rate is defined in the I2CxDIV MMR as follows: /(LOW + HIGH + 3) I2CCLK where: /I2CCD. I2CCLK PCLK is the peripheral clock, 20 MHz. PCLK I2CCD is the clock divide value and is set by the CLKCON1[10:8] bits.
  • Page 104 UG-498 ADuCM320 Hardware Reference Manual C Slave Mode Late Loading of I2CSTX Issue If a byte with the MSB equal to 0 is loaded into I2CxSTX just after the ninth rising edge of SCL during a read operation, the I C slave pulls the SDA pin low and holds it indefinitely.

  • Page 105: Register Summary: I2C0

    ADuCM320 Hardware Reference Manual UG-498 REGISTER SUMMARY: I2C0 Table 135. I2C0 Register Summary Address Name Description Reset 0x40003000 I2C0MCON Master control register 0x0000 0x40003004 I2C0MSTA Master status register 0x6000 0x40003008 I2C0MRX Master receive data register 0x0000 0x4000300C I2C0MTX Master transmit data register...
  • Page 106 UG-498 ADuCM320 Hardware Reference Manual Bits Bit Name Description Reset Access RESERVED Reserved. A value of 0 should be written to this bit. LOOPBACK Internal loopback enable. Note that is also possible for the master to loop back a transfer to the slave as long as the device address corresponds, that is, external loopback.
  • Page 107 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access NACKADDR ACK not received in response to an address. This bit asserts if an ACK is not received in response to an address. If IENACK is 1, an interrupt is generated when this bit asserts.
  • Page 108 UG-498 ADuCM320 Hardware Reference Manual Master Current Receive Data Count Register Address: 0x40003014, Reset: 0x0000, Name: I2C0MCRXCNT Table 141. Bit Descriptions for I2C0MCRXCNT Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. [7:0] COUNT Current receive count. This register gives the total number of bytes received so far.
  • Page 109 ADuCM320 Hardware Reference Manual UG-498 Slave Control Register Address: 0x40003028, Reset: 0x0000, Name: I2C0SCON Table 145. Bit Descriptions for I2C0SCON Bits Bit Name Description Reset Access RESERVED Reserved. STXDMA Enable slave Tx DMA request. Set to 1 by user code to enable I2C0 slave DMA Rx requests.
  • Page 110 UG-498 ADuCM320 Hardware Reference Manual Slave I2C0 Status/Error/IRQ Register Address: 0x4000302C, Reset: 0x0001, Name: I2C0SSTA Table 146. Bit Descriptions for I2C0SSTA Bits Bit Name Description Reset Access RESERVED Reserved. START Start and matching address. This bit is asserted if a start is detected on...
  • Page 111 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access STXREQ Slave transmit request. If EARLYTXR = 0, STXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit remains asserted.
  • Page 112 UG-498 ADuCM320 Hardware Reference Manual First Slave Address Device ID Register Address: 0x4000303C, Reset: 0x0000, Name: I2C0ID0 Table 150. Bit Descriptions for I2C0ID0 Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. [7:0] Slave device ID 0. I2C0ID0[7:1] is programmed with the device ID.
  • Page 113 ADuCM320 Hardware Reference Manual UG-498 Master and Slave FIFO Status Register Address: 0x4000304C, Reset: 0x0000, Name: I2C0FSTA Table 154. Bit Descriptions for I2C0FSTA Bits Bit Name Description Reset Access [15:10] RESERVED Reserved. MFLUSH Flush the master transmit FIFO. 0: clearing to 0 has no effect.

  • Page 114: Register Summary: I2C1

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: I2C1 Table 156. I2C1 Register Summary Address Name Description Reset 0x40003400 I2C1MCON Master control register 0x0000 0x40003404 I2C1MSTA Master status register 0x6000 0x40003408 I2C1MRX Master receive data register 0x0000 0x4000340C I2C1MTX Master transmit data register...
  • Page 115 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access RESERVED Reserved. A value of 0 should be written to this bit. LOOPBACK Internal loopback enable. Note that is also possible for the master to loop back a transfer to the slave as long as the device address corresponds, i.e.
  • Page 116 UG-498 ADuCM320 Hardware Reference Manual Bits Bit Name Description Reset Access NACKADDR ACK not received in response to an address. This bit asserts if an ACK is not received in response to an address. If IENACK is 1, an interrupt is generated when this bit asserts.
  • Page 117 ADuCM320 Hardware Reference Manual UG-498 Master Current Receive Data Count Register Address: 0x40003414, Reset: 0x0000, Name: I2C1MCRXCNT Table 162. Bit Descriptions for I2C1MCRXCNT Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. [7:0] COUNT Current receive count. This register gives the total number of bytes received so far.
  • Page 118 UG-498 ADuCM320 Hardware Reference Manual Slave Control Register Address: 0x40003428, Reset: 0x0000, Name: I2C1SCON Table 166. Bit Descriptions for I2C1SCON Bits Bit Name Description Reset Access RESERVED Reserved. STXDMA Enable slave Tx DMA request. Set to 1 by user code to enable I C slave DMA Rx requests.
  • Page 119 ADuCM320 Hardware Reference Manual UG-498 Slave I C Status/Error/IRQ Register Address: 0x4000342C, Reset: 0x0001, Name: I2C1SSTA Table 167. Bit Descriptions for I2C1SSTA Bits Bit Name Description Reset Access RESERVED Reserved. START Start and matching address. This bit is asserted if a start is detected on...
  • Page 120 UG-498 ADuCM320 Hardware Reference Manual Bits Bit Name Description Reset Access STXREQ Slave transmit request. If EARLYTXR = 0, STXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit remains asserted.
  • Page 121 ADuCM320 Hardware Reference Manual UG-498 First Slave Address Device ID Register Address: 0x4000343C, Reset: 0x0000, Name: I2C1ID0 Table 171. Bit Descriptions for I2C1ID0 Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. [7:0] Slave device ID 0. I2CID0[7:1] is programmed with the device ID. I2CID0[0] is don't care.
  • Page 122 UG-498 ADuCM320 Hardware Reference Manual Master and Slave FIFO Status Register Address: 0x4000344C, Reset: 0x0000, Name: I2C1FSTA Table 175. Bit Descriptions for I2C1FSTA Bits Bit Name Description Reset Access [15:10] RESERVED Reserved. MFLUSH Flush the master transmit FIFO. 0: clearing to 0 has no effect.

  • Page 123: Serial Peripheral Interfaces

    ADuCM320 Hardware Reference Manual UG-498 SERIAL PERIPHERAL INTERFACES SPI FEATURES Two complete hardware serial peripheral interfaces with the following standard SPI features: • Serial clock phase mode and serial clock polarity mode • LSB first transfer option • Loopback mode •...

  • Page 124: Spi Transfer Initiation

    UG-498 ADuCM320 Hardware Reference Manual In both master and slave mode, data is transmitted on one edge of the SCLK signal and sampled on the other. Therefore, it is important that the polarity and phase be configured the same for the master and slave devices.
  • Page 125 ADuCM320 Hardware Reference Manual UG-498 CLOCK CYCLE NUMBER SPI CLOCK (CPOL = 0) SPI CLOCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) Figure 22. SPI Transfer Protocol CPHA = 0 CLOCK CYCLE NUMBER SPI CLOCK (CPOL = 0)

  • Page 126: Spi Interrupts

    UG-498 ADuCM320 Hardware Reference Manual SPI INTERRUPTS There is one interrupt line per SPI and four sources of interrupts. SPIxSTA[0] reflects the state of the interrupt line, and SPIxSTA[7:4] reflects the state of the four sources. The SPI generates either TIRQ or RIRQ. Both interrupts cannot be enabled at the same time. The appropriate interrupt is enabled using the TIM bit, SPIxCON[6].

  • Page 127: Spi Wire-Or'ed Mode (Wom)

    ADuCM320 Hardware Reference Manual UG-498 SPI WIRE-OR’ED MODE (WOM) To prevent contention when the SPI is used in a multimaster or multislave system, the data output pins, MOSI and MISO, can be configured to behave as open-circuit drivers. An external pull-up resistor is required when this feature is selected. The WOM bit (SPIxCON[4]) controls the pad enable outputs for the data lines.

  • Page 128: Spi And Power-Down Modes

    UG-498 ADuCM320 Hardware Reference Manual Performing SPIx DMA Master Receive The DMA SPI Rx channel should be configured. The NVIC should be configured to enable DMA Rx master interrupt (for example, enable DMA Rx master interrupt SPI1 Rx using ISER0[29]).
  • Page 129 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access [10:8] RXFSTA SPI Rx FIFO status. 000: Rx FIFO empty 001: 1 valid byte in FIFO 010: 2 valid bytes in the FIFO 011: 3 valid bytes in the FIFO...

  • Page 130: Changes To Table 182

    UG-498 ADuCM320 Hardware Reference Manual Baud Rate Selection Register Address: 0x4002C00C, Reset: 0x0000, Name: SPI0DIV Table 182. Bit Descriptions for SPI0DIV Bits Bit Name Description Reset Access [15:9] RESERVED Reserved. CSIRQ_EN Enable interrupt on every CS edge in CONT mode. If this bit is set and the SPI module is in continuous mode, any edge on CS generates an interrupt and the corresponding status bits (CSRSG, CSFLG) are asserted.
  • Page 131 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access LOOPBACK Loopback enable. 0: cleared by user to be in normal mode. 1: set by user to connect MISO to MOSI and test software. Slave MISO output enable. 0: clear this bit to disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear.

  • Page 132: Register Summary: Spi1

    UG-498 ADuCM320 Hardware Reference Manual SPI DMA Enable Register Address: 0x4002C014, Reset: 0x0000, Name: SPI0DMA Table 184. Bit Descriptions for SPI0DMA Bits Bit Name Description Reset Access [15:3] RESERVED Reserved. IENRXDMA Enable receive DMA request. 0: disable RX DMA interrupt...
  • Page 133 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access CSFLG Detected a falling edge on CS, in CONT mode. This bit causes an interrupt. This can be used to identify the start of an SPI data frame. 0: cleared to 0 when the status register is read.
  • Page 134 UG-498 ADuCM320 Hardware Reference Manual Receive Register Address: 0x40030004, Reset: 0x0000, Name: SPI1RX Table 188. Bit Descriptions for SPI1RX Bits Bit Name Description Reset Access [15:8] DMA_DATA_BYTE_2 8-bit receive buffer. These 8-bits are used only in the DMA mode, where all FIFO accesses happen as half-word access.
  • Page 135 ADuCM320 Hardware Reference Manual UG-498 SPI Configuration Register Address: 0x40030010, Reset: 0x0000, Name: SPI1CON Table 191. Bit Descriptions for SPI1CON Bits Bit Name Description Reset Access [15:14] SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
  • Page 136 UG-498 ADuCM320 Hardware Reference Manual Bits Bit Name Description Reset Access LSB first transfer enable. 0: MSB transmitted first 1: LSB transmitted first SPI wired Or mode. 0: normal output levels 1: enables open circuit data output enable. External pull-ups required on...

  • Page 137: Uart Serial Interface

    ADuCM320 Hardware Reference Manual UG-498 UART SERIAL INTERFACE UART FEATURES • Industry-standard 16,450 UART peripheral • Support for DMA UART OVERVIEW The UART peripheral is a full-duplex universal asynchronous receiver/transmitter (UART), compatible with the industry-standard 16,450. The UART is responsible for converting data between serial and parallel formats. The serial communication follows an asynchronous protocol, supporting various word lengths, stop bits, and parity generation options.
  • Page 138 UG-498 ADuCM320 Hardware Reference Manual Polling the status flag is processor intensive and not typically used unless the system can tolerate the overhead. Interrupts can be disabled using the COMIEN register. Writing COMTX when it is not empty or reading COMRX when it is not full produces incorrect results and should not be done. In the former case, COMTX is overwritten by the new word, and the previous word is never transmitted.
  • Page 139 ADuCM320 Hardware Reference Manual UG-498 desc.ctrlcfg.bits.r_power = 0; Desc.ctrlCfg.Bits.src_prot_ctrl = 0x0; Desc.ctrlCfg.Bits.dst_prot_ctrl = 0x0; Desc.ctrlCfg.Bits.src_size = DMA_SIZE_BYTE; Desc.ctrlCfg.Bits.dst_size = DMA_SIZE_BYTE; // Rx primary descriptor Desc.srcEndPtr = (unsigned int)(&pADI_UART->COMRX); Desc.destEndPtr = (unsigned int)(pucTX_DMA + (iNumVals - 0x1)); Desc.ctrlCfg.Bits.n_minus_1 = iNumRX - 0x1;...
  • Page 140 UG-498 ADuCM320 Hardware Reference Manual Desc.destEndPtr = (unsigned int)(&pADI_UART->COMTX); Desc.ctrlCfg.Bits.n_minus_1 = iNumRX - 0x1; Desc.ctrlCfg.Bits.src_inc = DMA_SRCINC_BYTE; Desc.ctrlCfg.Bits.dst_inc = DMA_DSTINC_NO; *Dma_GetDescriptor(UARTTX_C) = Desc; // UART DMA Tx IRQ handler void DMA_UART_TX_Int_Handler() NVIC_DisableIRQ(DMA_UART_TX_IRQn); // Clear interrupt source Rev. C | Page 140 of 196...

  • Page 141: Register Summary: Uart

    ADuCM320 Hardware Reference Manual UG-498 REGISTER SUMMARY: UART Table 194. UART Register Summary Address Name Description Reset 0x40005000 COMTX Transmit holding register 0x0000 0x40005000 COMRX Receive buffer register 0x0000 0x40005004 COMIEN Interrupt enable register 0x0000 0x40005008 COMIIR Interrupt identification register...
  • Page 142 UG-498 ADuCM320 Hardware Reference Manual Bits Bit Name Description Reset Access EDMAT DMA requests in transmit mode. 0: DMA requests are disabled 1: DMA requests are enabled EDSSI Modem status interrupt. Interrupt is generated when any of COMMSR[3:0] are set.
  • Page 143 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access Parity enable. Used to control of the parity bit transmitted and checked. The value transmitted and the value checked are based on the settings of EPS and SP. 0: parity is not transmitted or checked...
  • Page 144 UG-498 ADuCM320 Hardware Reference Manual Line Status Register Address: 0x40005014, Reset: 0x0060, Name: COMLSR Table 201. Bit Descriptions for COMLSR Bits Bit Name Description Reset Access [15:7] RESERVED TEMT COMTX and shift register empty status. 0: COMTX has been written to and contains data to be transmitted. Care should be taken not to overwrite its value.
  • Page 145 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access DDCD Delta DCD. If set, this bit self clears after COMMSR is read. 0: DCD has not changed state since COMMSR was last read 1: DCD changed state since COMMSR last read TERI Trailing edge RI.

  • Page 146: Pla

    UG-498 ADuCM320 Hardware Reference Manual PLA FEATURES ADuCM320 integrates a fully programmable logic array (PLA) that consists of four independent but interconnected PLA blocks. Each block consists of eight PLA elements: Block X Element 0 to Block X Element 7, where X is the block number. Each ADuCM320 four blocks, resulting in a total of 32 PLA elements: Element 0 to Element 31.

  • Page 147: Pla Operation

    ADuCM320 Hardware Reference Manual UG-498 PLA OPERATION The PLA is configured via a set of user MMRs. The output(s) of the PLA can be routed to the internal interrupt system, to the PLA_DOUTx MMRs, or to any of the 14 PLA output pins.
  • Page 148 UG-498 ADuCM320 Hardware Reference Manual BLOCK 2 BLOCK 0 OUTPUT ELEMENT (n – 16) BLOCK 2 ELEMENT 0 (ELEMENT 16) BLOCK 0 ELEMENT 0 (ELEMENT 0) OUTPUT OUTPUT BLOCK 2 ELEMENT 7 BLOCK 0 ELEMENT 7 (ELEMENT 23) (ELEMENT 7)
  • Page 149 ADuCM320 Hardware Reference Manual UG-498 Table 206. Element GPIO Input/Output PLA Block 0 PLA Block 1 PLA Block 2 PLA Block 3 Element Input Output Element Input Output Element Output Element Output P0.0 P2.0 P0.1 P0.2 P0.4 P2.2 P1.4 P2.4 P3.4...

  • Page 150: Register Summary: Pla

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: PLA Table 210. PLA Register Summary Address Name Description Reset 0x40005800 PLA_ELEMn ELEMx configuration register. 0x0000 0x40005880 PLA_CLK PLA clock select. 0x0000 0x40005884 PLA_IRQ0 Interrupt register for Block 0 and Block 1. 0x0000...
  • Page 151 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access MUX4 Select or bypass flip-flop output. 0: FF output 1: bypass output PLA Clock Select Register Address: 0x40005880, Reset: 0x0000, Name: PLA_CLK Table 212. Bit Descriptions for PLA_CLK Bits...
  • Page 152 UG-498 ADuCM320 Hardware Reference Manual Interrupt Register for Block 0 and Block 1 Address: 0x40005884, Reset: 0x0000, Name: PLA_IRQ0 Table 213. Bit Descriptions for PLA_IRQ0 Bits Bit Name Description Reset Access [15:13] RESERVED Not used. Reserved IRQ1_EN IRQ1 enable. 0: disable IRQ1 interrupt...
  • Page 153 ADuCM320 Hardware Reference Manual UG-498 Data Output for Block 0 and Block 1 Register Address: 0x40005898, Reset: 0x0000, Name: PLA_DOUT0 Table 217. Bit Descriptions for PLA_DOUT0 Bits Bit Name Description Reset Access [15:0] DOUT Output bit from Element 15 to Element 0.

  • Page 154: General-Purpose Timers

    UG-498 ADuCM320 Hardware Reference Manual GENERAL-PURPOSE TIMERS GENERAL-PURPOSE TIMERS FEATURES  Three identical general-purpose, 16-bit count-up/count-down timers Timer 0, Timer 1, and Timer 2  Clocked from five different clock sources Peripheral clock (PCLK) 80 MHz system clock (HCLK) 32 kHz internal oscillator (LFOSC) 16 MHz external crystal (HFXTAL) or internal 16 MHz oscillator (HFOSC), depending on the value in CLKCON0[11].

  • Page 155: General-Purpose Timers Operation

    ADuCM320 Hardware Reference Manual UG-498 GENERAL-PURPOSE TIMERS OPERATION Free Running Mode In free running mode, the timer is started by setting the enable bit (TxCON[4]) to 1 and the MOD bit (TxCON[3]) to 0. The timer increments from zero scale/full scale to full scale/zero scale if counting up/down. Full scale is 2 –...
  • Page 156 UG-498 ADuCM320 Hardware Reference Manual Capture Event Function There are several interrupt events that can be captured by the general-purpose timers. These events are shown in Table 220. Any one of the events associated with a general-purpose timer can cause a capture of the 16-bit TxVAL register into the 16-bit TxCAP register.

  • Page 157: Register Summary: General-Purpose Timer 0

    ADuCM320 Hardware Reference Manual UG-498 REGISTER SUMMARY: GENERAL-PURPOSE TIMER 0 Table 221. Timer 0 Register Summary Address Name Description Reset 0x40000000 T0LD 16-bit load value register 0x0000 0x40000004 T0VAL 16-bit timer value register 0x0000 0x40000008 T0CON Control register 0x000A 0x4000000C...
  • Page 158 UG-498 ADuCM320 Hardware Reference Manual Bits Bit Name Description Reset Access Timer mode. This bit is used to control whether the timer runs in periodic or free running mode. In periodic mode the up/down counter starts at the defined LOAD value (T0LD); in free running mode, the up/down counter starts at 0x0000 or 0xFFFF depending on whether the timer is counting up or down.
  • Page 159 ADuCM320 Hardware Reference Manual UG-498 Status Register Address: 0x4000001C, Reset: 0x0000, Name: T0STA Table 227. Bit Descriptions for T0STA Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. PDOK T0CLRI synchronization. This bit is set automatically when the user sets T0CLRI[0] = 1.

  • Page 160: Register Summary: General-Purpose Timer 1

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: GENERAL-PURPOSE TIMER 1 Table 228. Timer 1 Register Summary Address Name Description Reset 0x40000400 T1LD 16-bit load value register 0x0000 0x40000404 T1VAL 16-bit timer value register 0x0000 0x40000408 T1CON Control register 0x000A 0x4000040C...
  • Page 161 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access Timer mode. This bit is used to control whether the timer runs in periodic or free running mode. In periodic mode, the up/down counter starts at the defined LOAD value (T1LD); in free running mode, the up/down counter starts at 0x0000 or 0xFFFF depending on whether the timer is counting up or down.
  • Page 162 UG-498 ADuCM320 Hardware Reference Manual Status Register Address: 0x4000041C, Reset: 0x0000, Name: T1STA Table 234. Bit Descriptions for T1STA Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. PDOK T1CLRI synchronization. This bit is set automatically when the user sets T1CLRI[0] = 1.

  • Page 163: Register Summary: General-Purpose Timer 2

    ADuCM320 Hardware Reference Manual UG-498 REGISTER SUMMARY: GENERAL-PURPOSE TIMER 2 Table 235. Timer 2 Register Summary Address Name Description Reset 0x40000800 T2LD 16-bit load value register 0x0000 0x40000804 T2VAL 16-bit timer value register 0x0000 0x40000808 T2CON Control register 0x000A 0x4000080C...
  • Page 164 UG-498 ADuCM320 Hardware Reference Manual Bits Bit Name Description Reset Access Timer mode. This bit is used to control whether the timer runs in periodic or free running mode. In periodic mode, the up/down counter starts at the defined LOAD value (T2LD); in free running mode, the up/down counter starts at 0x0000 or 0xFFFF depending on whether the timer is counting up or down.
  • Page 165 ADuCM320 Hardware Reference Manual UG-498 Status Register Address: 0x4000081C, Reset: 0x0000, Name: T2STA Table 241. Bit Descriptions for T2STA Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. PDOK T2CLRI synchronization. This bit is set automatically when the user sets T2CLRI[0] = 1.

  • Page 166: Watchdog Timer

    UG-498 ADuCM320 Hardware Reference Manual WATCHDOG TIMER WATCHDOG TIMER FEATURES 16-bit count-down timer, which can be used to recover from an invalid software state. Clocked by the 32 kHz internal oscillator (LFOSC) with a programmable prescaler (1, 16, 256, or 4096).

  • Page 167: Register Summary: Watchdog Timer

    ADuCM320 Hardware Reference Manual UG-498 REGISTER SUMMARY: WATCHDOG TIMER Table 242. Watchdog Timer Register Summary Address Name Description Reset 0x40002580 T3LD Load value register 0x1000 0x40002584 T3VAL Current count value register 0x1000 0x40002588 T3CON Control register 0x00E9 0x4000258C T3CLRI Clear interrupt register...
  • Page 168 UG-498 ADuCM320 Hardware Reference Manual Clear Interrupt Register Address: 0x4000258C, Reset: 0x0000, Name: T3CLRI Table 246. Bit Descriptions for T3CLRI Bits Bit Name Description Reset Access [15:0] CLRWDG Clear watchdog. User writes 0xCCCC to reset/reload/restart T3 or clear IRQ. A write of any other value causes a watchdog reset.

  • Page 169: Wake-Up Timer

    ADuCM320 Hardware Reference Manual UG-498 WAKE-UP TIMER WAKE-UP TIMER FEATURES  32-bit counter (count down or count up)  Three clock sources with programmable prescaler (1, 16, 256, or 32768) Peripheral clock (PCLK) 32 kHz internal oscillator (LFOSC) External clock applied on Pin P1.0 (ECLKIN) ...
  • Page 170 UG-498 ADuCM320 Hardware Reference Manual Compare Field Registers Hardware Updated Field T4INC is a 12-bit interval register that is used to update the compare value in T4WUFAx by hardware. When a new value is written in T4INC, Bits[16:5] of the internal 32-bit compare register (T4WUFAx) are loaded with the new T4INC value. If the new compare value is less than the T4WUFD value in periodic mode or less than 0xFFFFFFFF in free running mode, this 32-bit compare register is automatically incremented with the contents of T4INC (shifted by five) each time the wake-up counter reaches the value in this compare register.
  • Page 171 ADuCM320 Hardware Reference Manual UG-498 Interrupts/Wake-Up Signals An interrupt is generated when the counter value corresponds to any of the compare points or full scale in free running mode. The timer continues counting or is reset to 0. The wake-up timer generates five maskable interrupts. They are enabled in the T4IEN register. Interrupts can be cleared by setting the corresponding bit in the T4CLRI register.

  • Page 172: Register Summary: Wake-Up Timer

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: WAKE-UP TIMER Table 248. Wake-Up Timer Register Summary Address Name Description Reset 0x40002500 T4VAL0 Current count value—least significant 16 bits 0x0000 0x40002504 T4VAL1 Current count value—most significant 16 bits 0x0000 0x40002508 T4CON Control register...
  • Page 173 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access ENABLE Timer enable. 0: DIS: disable the timer (default) 1: EN: enable the timer Timer mode. 0: PERIODIC: cleared by user to operate in periodic mode. In this mode, the timer counts up to T4WUFD.
  • Page 174 UG-498 ADuCM320 Hardware Reference Manual Wake-Up Field C—Most Significant 16 Bits Register Address: 0x4000251C, Reset: 0x0000, Name: T4WUFC1 Table 256. Bit Descriptions for T4WUFC1 Bits Bit Name Description Reset Access [15:0] T4WUFCH Wake-Up Field C High. Most significant 16 bits of Wake-Up Field C.
  • Page 175 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access IRQCRY Wake-up status to power-down. Set automatically when any of the interrupts are still set in the external crystal clock domain. Cleared automatically when the interrupts are cleared, allowing power down mode.

  • Page 176: Pwm

    UG-498 ADuCM320 Hardware Reference Manual PWM FEATURES • 8-channel PWM interface • H-bridge mode supported on 2 pairs PWM OVERVIEW ADuCM320 integrates an 8-channel PWM interface. Eight channels are grouped as three pairs (0 to 3). The first two pairs of PWM outputs (PWM0, PWM1, PWM2, and PWM3) can be configured in standard mode or to drive an H-bridge.
  • Page 177 ADuCM320 Hardware Reference Manual UG-498 PAIR 0 TIMER 0xFFFF PWM0LEN PWM0COM0 PWM0COM1 PWM0COM2 0x0000 PWM0COM2 PWM0COM1 PWM0COM0 PWM0LEN PAIR 0 OUTPUTS PWM0 HIGH SIDE PWM1 LOW SIDE NOTES 1. NOTE THAT THE HIGH-SIDE PWM OUTPUT FOR EACH CHANNEL MUST HAVE A HIGH DURATION PERIOD GREATER THAN OR EQUAL TO THE HIGH PERIOD DURATION OF THE LOW-SIDE OUTPUT.
  • Page 178 UG-498 ADuCM320 Hardware Reference Manual Standard Mode In standard mode, each pair is individually controlled by a selection of registers, as shown in Table 266. Table 266. Compare Register Descriptions in Standard Mode (Base Address: 0x40024000) Pair Name Description PWM0COM0 PWM0 output goes high when the PWM timer reaches the count value stored in this register.

  • Page 179: Pwm Interrupt Generation

    ADuCM320 Hardware Reference Manual UG-498 H-Bridge Mode In H-bridge mode, the period and duty cycle of the four outputs are controlled using the Pair 0 registers: PWM0COM0, PWM0COM1, PWM0COM2, and PWM0LEN. In addition, the state of the output is controlled by PWMCON0 Bit 9, Bit 5, Bit 4, and Bit 2, as summarized in Table 267.

  • Page 180: Register Summary: Pwm

    UG-498 ADuCM320 Hardware Reference Manual REGISTER SUMMARY: PWM Table 268. PWM Register Summary Address Name Description Reset 0x40024000 PWMCON0 PWM control register 0x0012 0x40024004 PWMCON1 ADC conversion start and trip control register 0x0000 0x40024008 PWMICLR Hardware trip configuration register 0x0000...
  • Page 181 ADuCM320 Hardware Reference Manual UG-498 Bits Bit Name Description Reset Access LCOMP Signal to load a new set of compare register values. In standard mode, this bit is cleared when the new values are loaded in the compare registers for all the channels.
  • Page 182 UG-498 ADuCM320 Hardware Reference Manual Compare Register 2 for PWM0 and PWM1 Address: 0x40024018, Reset: 0x0000, Name: PWM0COM2 Table 274. Bit Descriptions for PWM0COM2 Bits Bit Name Description Reset Access [15:0] COM2 Compare Register 2 data. Period Value Register for PWM0 and PWM1 Address: 0x4002401C, Reset: 0x0000, Name: PWM0LEN Table 275.
  • Page 183 ADuCM320 Hardware Reference Manual UG-498 Compare Register 1 for PWM4 and PWM5 Address: 0x40024034, Reset: 0x0000, Name: PWM2COM1 Table 281. Bit Descriptions for PWM2COM1 Bits Bit Name Description Reset Access [15:0] COM1 Compare Register 1 data. Compare Register 2 for PWM4 and PWM5 Address: 0x40024038, Reset: 0x0000, Name: PWM2COM2 Table 282.

  • Page 184: Added Mdio Interrupt Power-Up Register Write Sequence Section

    UG-498 ADuCM320 Hardware Reference Manual MDIO MDIO FEATURES The MDIO interface hardware can receive complete MDIO frames without software intervention. The MDIO interface hardware can also transmit complete MDIO frames without software intervention as long as the data to be sent is provided before receiving the turnaround bits (TA) of the read or post read increment address frame.
  • Page 185 ADuCM320 Hardware Reference Manual UG-498 Table 288. Frame Details for Different Frame Types Management Frame Fields Frame Idle PHYADR DEVADD Address/Data Idle Write Address 1…1 aaaaa aaaaa aaaaaaaaaaaaaaaa Write Data 1…1 aaaaa aaaaa dddddddddddddddd Read Data 1…1 aaaaa aaaaa dddddddddddddddd Post Read Increment Address 1…1...

  • Page 186: Block Switching

    UG-498 ADuCM320 Hardware Reference Manual MDIO Interrupt Power-Up Register Write Sequence To avoid false MDIO interrupts on startup, the order of register writes is important. The following is a code example showing how to correctly configure the MDIO interrupt on startup.
  • Page 187 ADuCM320 Hardware Reference Manual UG-498 Flash Block Partitioning In the MDIO dual program image configuration, the Program Image A in Flash 0 and the NVR Data Block A in Flash 1 should be used together or, alternatively, the Program Image B in Flash 1 and the NVR Data Block B in Flash 0 should be used together. Because the data and code are in different flash blocks, the code can continue executing in the active program image while flash operations are performed on the associated NVR data flash block.
  • Page 188 UG-498 ADuCM320 Hardware Reference Manual Trial Run Mode After user code is entered, the code checks whether a trial run or a normal run should be performed. A trial run is indicated if the active Key1 is less than the other Key1’ . In a trial run, the old code first checks that the new program image is functioning correctly. The trial run starts in the old program image and performs initial checks, such as CRCs and other checks that the user deems necessary, on the new program image.
  • Page 189 ADuCM320 Hardware Reference Manual UG-498 RESET HARDWARE SWITCH TO FLASH 1 KERNEL CODE P2.3 = HIGH K1B0 < K1B1 K2B0 = 0 K2B1 = 0 K2B1 = 0 K2B0 = 0 DOWNLOADER SWITCH TO FLASH 1 CHANGE TO USER CODE USER CODE KEY1’...
  • Page 190 UG-498 ADuCM320 Hardware Reference Manual Table 291. Definition of Keys 1, 2 Description K1B0 Key1 in Flash Block 0 at 0x1DFE0. K1B1 Key1 in Flash Block 1 at 0x3DFE0. K2B0 Key2 in Flash Block 0 at 0x1DFE8. K2B1 Key2 in Flash Block 1 at 0x3DFE8.

  • Page 191: Register Summary: Mdio Interface (Mdio)

    ADuCM320 Hardware Reference Manual UG-498 REGISTER SUMMARY: MDIO INTERFACE (MDIO) Names and short descriptions of bits refer to the active state represented by a high (1) level unless explicitly enumerated. Table 292. MDIO Register Summary Address Name Description Reset Access...
  • Page 192 UG-498 ADuCM320 Hardware Reference Manual MDIO Received Address Register Address: 0x40005C0C, Reset: 0x000X, Name: MDADR Data received from last address frame. Table 296. Bit Descriptions for MDADR Bits Bit Name Description Reset Access [15:0] MD_ADR Received address. MDIO Data for Transmission Register Address: 0x40005C10, Reset: 0x0000, Name: MDTXD Data to be transmitted by next Data frame.
  • Page 193 ADuCM320 Hardware Reference Manual UG-498 MDIO Interrupt Enables Register Address: 0x40005C1C, Reset: 0x0000, Name: MDIEN Enables interrupts on specified events. Table 300. Bit Descriptions for MDIEN Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. MD_PHYNI If set, interrupt is requested when MD_PHYN becomes active.

  • Page 194: Hardware Design Considerations

    UG-498 ADuCM320 Hardware Reference Manual HARDWARE DESIGN CONSIDERATIONS TYPICAL SYSTEM CONFIGURATION Figure 39 shows a typical ADuCM320 configuration. The figure illustrates some of the hardware considerations. The four 0.47 µF capacitors on DVDD_REG1, DVDD_REG2, AVDD_REG1, and AVDD_REG2 should be placed as close as possible to the pins. VDD1 should either have a separate power supply or should be filtered from the other digital supply using an inductor bead and a resistor.
  • Page 195 ADuCM320 Hardware Reference Manual UG-498 DVDD VDD1 0.47µF 0.47µF VDD1 RESET 10kΩ RESET XTALI VDD1 XTALO 10kΩ PVDD P2.3/BM PVDD0 PVDD1 P1.0/SIN PVDD2 ADuCM320 SWCLK PVDD3 CDAMP0 P1.1/SOUT CDAMP1 SWDIO CDAMP2 CDAMP3 AVDD 0.47µF 3.16kΩ 4.7µF 0.47µF 0.47µF AGND RESET...

  • Page 196: Rev. C

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