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ADuCM320 Hardware Reference Manual
Bits
Bit Name
[7:5]
RESERVED
4
EN
[3:2]
RESERVED
[1:0]
RN
DAC2 Control Register
Address: 0x40082408, Reset: 0x0100, Name: DAC2CON
Table 39. Bit Descriptions for DAC2CON
Bits
Bit Name
[15:9]
RESERVED
8
PD
[7:5]
RESERVED
4
EN
[3:2]
RESERVED
[1:0]
RN
DAC3 Control Register
Address: 0x4008240C, Reset: 0x0100, Name: DAC3CON
Table 40. Bit Descriptions for DAC3CON
Bits
Bit Name
[15:9]
RESERVED
8
PD
[7:5]
RESERVED
4
EN
[3:2]
RESERVED
[1:0]
RN
Description
Reserved.
DAC1 enable. Must be set to high.
0: DAC disable. Clear DAC data immediately.
1: DAC enable.
Reserved.
DAC1 reference selection. These bits set the DAC range. A write to these
bits has immediate effect on the DAC.
00: internal reference
01: reserved
10: reserved
11: AVDD/AGND
Description
Reserved.
DAC2 power down.
0: DAC2 is powered up
1: DAC2 is powered down and output is floating
Reserved.
DAC2 enable. Must be set to high.
0: DAC disable. Clear DAC data immediately
1: DAC enable.
Reserved.
DAC2 reference selection. These bits set the DAC range. A write to these
bits has immediate effect on the DAC.
00: internal reference
01: reserved
10: reserved
11: AVDD/AGND
Description
Reserved.
DAC3 power down.
0: DAC3 is powered up
1: DAC3 is powered down and output is floating
Reserved.
DAC3 enable. Must be set to high.
0: DAC disable. Clear DAC data immediately
1: DAC enable.
Reserved.
DAC3 reference selection. These bits set the DAC range. A write to these
bits has immediate effect on the DAC.
00: internal reference
01: reserved
10: reserved
11: AVDD/AGND
Rev. C | Page 45 of 196
UG-498
Reset
Access
0x0
RW
0x0
RW
0x0
RW
0x0
RW
Reset
Access
0x0
R
0x1
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
Reset
Access
0x0
R
0x1
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
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