Register Summary: Spi1; Register Details: Spi1 - Analog Devices ADuCM320 Hardware Reference Manual

UG-498
SPI DMA Enable Register
Address: 0x4002C014, Reset: 0x0000, Name: SPI0DMA
Table 184. Bit Descriptions for SPI0DMA
Bits Bit Name
[15:3] RESERVED
2 IENRXDMA
1 IENTXDMA
0 ENABLE
Transfer Byte Count Register
Address: 0x4002C018, Reset: 0x0000, Name: SPI0CNT
Table 185. Bit Descriptions for SPI0CNT
Bits Bit Name
[15:8] RESERVED
[7:0] COUNT

REGISTER SUMMARY: SPI1

Table 186. SPI1 Register Summary
Address
0x40030000
0x40030004
0x40030008
0x4003000C
0x40030010
0x40030014
0x40030018

REGISTER DETAILS: SPI1

Status Register
Address: 0x40030000, Reset: 0x0000, Name: SPI1STA
Table 187. Bit Descriptions for SPI1STA
Bits Bit Name
15 RESERVED
14 CSRSG
Description
Reserved.
Enable receive DMA request.
0: disable RX DMA interrupt
1: enable RX DMA interrupt
Enable transmit DMA request.
0: disable TX DMA interrupt
1: enable TX DMA interrupt
Enable DMA for data transfer. Set by user code to start a DMA transfer.
Cleared by user code at the end of DMA transfer. This bit needs to be
cleared to prevent extra DMA request to the µDMA controller.
Description
Reserved.
Transfer byte count. COUNT indicates the number of bytes to be
transferred. Count is used in both receive and transmit transfer types. The
COUNT value assures that a master mode transfer terminates at the proper
time and that 16-bit DMA transfers are byte padded or discarded as
required to match odd transfer counts. Reset by clearing SPI0CON[0] or if
SPI0CNT is updated.
Name Description
SPI1STA Status register
SPI1RX Receive register
SPI1TX Transmit register
SPI1DIV Baud rate selection register
SPI1CON SPI configuration register
SPI1DMA SPI DMA enable register
SPI1CNT Transfer byte count register
Description
Reserved.
Detected a rising edge on CS, in CONT mode. This bit causes an interrupt.
This can be used to identify the end of an SPI data frame.
0: cleared to 0 when the status register is read
1: set to 1 when there was a rising edge in CS line, when the device was in
master mode, continuous transfer, high frequency mode and CSIRQ_EN
was asserted.
ADuCM320 Hardware Reference Manual
Rev. C | Page 132 of 196
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x0 RW
Reset RW
0x0000 R
0x0000 R
0x0000 W
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
Reset Access
0x0 R
0x0 RC