Analog Devices ADuCM320 Hardware Reference Manual page 162

UG-498
Status Register
Address: 0x4000041C, Reset: 0x0000, Name: T1STA
Table 234. Bit Descriptions for T1STA
Bits Bit Name
[15:8] RESERVED
7 PDOK
6 BUSY
[5:2] RESERVED
1 CAP
0 TMOUT
Description
Reserved.
T1CLRI synchronization. This bit is set automatically when the user sets
T1CLRI[0] = 1. It is cleared automatically when the clear interrupt request
has crossed clock domains and taken effect in the timer clock domain.
0: CLR. The interrupt is cleared in the timer clock domain.
1: SET. T1CLRI[0] is being updated in the timer clock domain.
Timer busy. This bit informs the user that a write to T1CON is still crossing
into the timer clock domain. This bit should be checked after writing
T1CON and further writes should be suppressed until this bit is cleared.
0: CLR. Timer ready to receive commands to T1CON.
1: SET. Timer not ready to receive commands to T1CON.
Reserved.
Capture event pending.
0: CLR. No capture event is pending.
1: SET. A capture event is pending.
Timeout event occurred. This bit set automatically when the value of the
counter reaches zero while counting down or reaches full scale when
counting up. This bit is cleared when T1CLRI[0] is set by the user.
0: CLR. No timeout event has occurred.
1: SET. A timeout event has occurred.
Rev. C | Page 162 of 196
ADuCM320 Hardware Reference Manual
Reset Access
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R