Analog Devices ADuCM320 Hardware Reference Manual page 192

UG-498
MDIO Received Address Register
Address: 0x40005C0C, Reset: 0x000X, Name: MDADR
Data received from last address frame.
Table 296. Bit Descriptions for MDADR
Bits Bit Name
[15:0] MD_ADR
MDIO Data for Transmission Register
Address: 0x40005C10, Reset: 0x0000, Name: MDTXD
Data to be transmitted by next Data frame.
Table 297. Bit Descriptions for MDTXD
Bits Bit Name
[15:0] MD_TXD
MDIO PHYADDR Software Values and Selection and DEVADD Register
Address: 0x40005C14, Reset: 0x0400, Name: MDPHY
Sets expected values for control part of frame.
Table 298. Bit Descriptions for MDPHY
Bits Bit Name
15 RESERVED
[14:10] MD_DEVADD
[9:5] MD_PHYSEL
[4:0] MD_PHYSW
MDIO Progress Signaling Through Frame Register
Address: 0x40005C18, Reset: 0x0000, Name: MDSTA
Indicates progress through frame.
Table 299. Bit Descriptions for MDSTA
Bits Bit Name
[15:8] RESERVED
7 MD_PHYN
6 MD_PHYM
5 MD_DEVN
4 MD_DEVM
3 MD_RDF
2 MD_INCF
1 MD_ADRF
0 MD_WRF
Description
Received address.
Description
Data that is to be transmitted by the next read or post read increment address
frame. Before a read frame, the master sends an address frame to specify which
data is to be read. After this address frame, the user software must place this
requested data into MD_TXD before it is required by the read frame. The time
available is at least 45 MDIO clock cycles being a minimum of the read frame
preamble and up to 3 cycles before TA. This is equivalent to 900 CPU clock cycles.
Description
Reserved.
Expected DEVADD. Normally 01.
Selects expected PHYADR bits. For each of the 5 bits:
0: sets expected PHYADR.x = PRTADRx pin.
1: sets expected PHYADR.x = MD_PHYSW.x.
Software provided PHYADR bits. Chosen according to corresponding
MD_PHYSEL bits.
Description
Reserved.
Set at end of PHYADR if PHYADR nonmatching. Cleared by reading MDSTA.
Set at end of PHYADR if PHYADR matching. Cleared by reading MDSTA.
Set at end of DEVADD if DEVADD nonmatching. Cleared by reading MDSTA.
Set at end of DEVADD if DEVADD matching. Cleared by reading MDSTA.
Set at end of Read frame if DEVADD and PHYADR are matching. Cleared by
reading MDSTA.
Set at end of post read increment address frame if DEVADD and PHYADR are
matching. Cleared by reading MDSTA.
Set at end of Address frame if DEVADD and PHYADR are matching. Cleared by
reading MDSTA.
Set at end of Write frame if DEVADD and PHYADR are matching. Cleared by
reading MDSTA.
Rev. C | Page 192 of 196
ADuCM320 Hardware Reference Manual
Reset Access
0xx R
Reset Access
0x0000 RW
Reset Access
0x0 R
0x1 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x0 RC
0x0 RC
0x0 RC
0x0 RC
0x0 RC
0x0 RC
0x0 RC
0x0 RC