Analog Devices ADuCM320 Hardware Reference Manual page 107

ADuCM320 Hardware Reference Manual
Bits Bit Name
4 NACKADDR
3 MRXREQ
2 MTXREQ
[1:0] MTXFSTA
Master Receive Data Register
Address: 0x40003008, Reset: 0x0000, Name: I2C0MRX
Table 138. Bit Descriptions for I2C0MRX
Bits Bit Name
[15:8] RESERVED
[7:0] ICMRX
Master Transmit Data Register
Address: 0x4000300C, Reset: 0x0000, Name: I2C0MTX
Table 139. Bit Descriptions for I2C0MTX
Bits Bit Name
[15:8] RESERVED
[7:0] I2C0MTX
Master Receive Data Count Register
Address: 0x40003010, Reset: 0x0000, Name: I2C0MRXCNT
Table 140. Bit Descriptions for I2C0MRXCNT
Bits Bit Name
[15:9] RESERVED
8 EXTEND
[7:0] COUNT
Description
ACK not received in response to an address. This bit asserts if an ACK is not
received in response to an address. If IENACK is 1, an interrupt is generated
when this bit asserts. This bit is cleared on a read of the I2C0MSTA register.
This bit can drive an interrupt.
Master receive request. This bit asserts when there is data in the receive
FIFO. If IENMRX is 1, an interrupt is generated when this bit asserts. This bit
can drive an interrupt.
Master transmit request. This bit asserts when the direction bit is 0 and the
transmit FIFO is either empty or not full. If IENMTX is 1, an interrupt is
generated when this bit asserts. This bit can drive an interrupt.
Master transmit FIFO status. These 2 bits show the master transmit FIFO
status and can be decoded as follows:
00 = FIFO empty
10 = 1 byte in FIFO
11 = FIFO full.
Description
Reserved.
Master receive register. This register allows access to the receive data FIFO.
The FIFO can hold 2 bytes.
Description
Reserved.
Master transmit register. For test and debug purposes, when read, this
register returns the byte that is currently being transmitted by the master.
That is a byte written to the transmit register can be read back some time
later when that byte is being transmitted on the line. This register allows
access to the transmit data FIFO. The FIFO can hold 2 bytes.
Description
Reserved.
Extended read. Use this bit if greater than 256 bytes are required on a read.
For example, to receive 412 bytes, write 0x100 (EXTEND = 1) to the
I2C0MRXCNT register. Wait for the first byte to be received, then check the
I2C0MCRXCNT register for every byte received thereafter. When COUNT
returns to 0, 256 bytes have been received. Then write 0x09C to the
I2C0MRXCNT register.
Receive count. Program the number of bytes required minus one to this
register. If just 1 byte is required, write 0 to this register. If greater than 256
bytes are required, use EXTEND.
Rev. C | Page 107 of 196
UG-498
Reset Access
0x0 RC
0x0 R
0x0 R
0x0 R
Reset Access
0x0 R
0x0 R
Reset Access
0x0 R
0x0 RW
Reset Access
0x0 R
0x0 RW
0x0 RW