Analog Devices ADuCM320 Hardware Reference Manual page 98

UG-498
GPIO Port Pull-Up Enable Registers
Address: 0x40020008, Reset: 0x00, Name: GP0PUL
Address: 0x40020048, Reset: 0x00, Name: GP1PUL
Address: 0x40020088, Reset: 0x08, Name: GP2PUL
Address: 0x400200C8, Reset: 0x00, Name: GP3PUL
Table 125. Bit Descriptions for GP0PUL, GP1PUL, GP2PUL, GP3PUL
Bits Bit Name
[7:0] PUL
GPIO Port Pull-Down Enable Registers
Address: 0x40020108, Reset: 0x00, Name: GP4PUL
Address: 0x40020248, Reset: 0x00, Name: GP5PUL
Table 126. Bit Descriptions for GP4PUL, GP5PUL
Bits Bit Name
[7:0] PUL
GPIO Port Input Path Enable Registers
Address: 0x4002000C, Reset: 0xFF, Name: GP0IE
Address: 0x4002004C, Reset: 0xFF, Name: GP1IE
Address: 0x4002008C, Reset: 0xFF, Name: GP2IE
Address: 0x400200CC, Reset: 0xFF, Name: GP3IE
Address: 0x4002010C, Reset: 0xFF, Name: GP4IE
Address: 0x4002024C, Reset: 0xF, Name: GP5IE
Table 127. Bit Descriptions for GP0IE, GP1IE, GP2IE, GP3IE, GP4IE, and GP5IE
Bits Bit Name
[7:0] IEN
GPIO Port Registered Data Input Registers
Address: 0x40020010, Reset: 0x0X, Name: GP0IN
Address: 0x40020050, Reset: 0x0X, Name: GP1IN
Address: 0x40020090, Reset: 0x0X, Name: GP2IN
Address: 0x400200D0, Reset: 0x0X, Name: GP3IN
Address: 0x40020110, Reset: 0x0X, Name: GP4IN
Address: 0x40020250, Reset: 0x0X, Name: GP5IN
Table 128. Bit Descriptions for GP0IN, GP1IN, GP2IN, GP3IN, GP4IN, and GP5IN
Bits Bit Name
[7:0] IN
Description
Pin pull-up enable in input mode.
0: Disable the pull up on the corresponding GPIO.
1: Enable the pull up on the corresponding GPIO.
Description
Pin pull-down enable in input mode.
0: disable the pull-down on the corresponding GPIO.
1: enable the pull-down on the corresponding GPIO.
Description
Input path enable.
0: disable the input path on the corresponding GPIO.
1: enable the input path on the corresponding GPIO.
Must be set for external interrupts and to read the pin value.
Description
Registered data input. Each bit reflects the state of the GPIO pin.
Rev. C | Page 98 of 196
ADuCM320 Hardware Reference Manual
Reset Access
See Table 122 RW
Reset Access
See Table 122 RW
Reset Access
See Table 122 RW
Reset Access
See Table 122 R